ADCMP604(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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ADCMP604
(Rev.:Rev0)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators

Analog Devices 

ADCMP604/ADCMP605

APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The ADCMP604/ADCMP605 comparators are very high speed

devices. Despite the low noise output stage, it is essential to use

proper high speed design techniques to achieve the specified

performance. Because comparators are uncompensated

amplifiers, feedback in any phase relationship is likely to cause

oscillations or undesired hysteresis. Of critical importance is the

use of low impedance supply planes, particularly the output

supply plane (VCCO) and the ground plane (GND). Individual

supply planes are recommended as part of a multilayer board.

Providing the lowest inductance return path for switching

currents ensures the best possible performance in the target

application.

It is also important to adequately bypass the input and output

supplies. Multiple high quality 0.01 μF bypass capacitors should

be placed as close as possible to each of the VCCI and VCCO supply

pins and should be connected to the GND plane with redundant

vias. At least one of these should be placed to provide a physically

short return path for output currents flowing back from ground

to the VCC pin. High frequency bypass capacitors should be

carefully selected for minimum inductance and ESR. Parasitic

layout inductance should also be strictly controlled to maximize

the effectiveness of the bypass at high frequencies.

If the package allows, and the input and output supplies have

been connected separately (VCCI ≠ VCCO), be sure to bypass each

of these supplies separately to the GND plane. Do not connect a

bypass capacitor between these supplies. It is recommended

that the GND plane separate the VCCI and VCCO planes when the

circuit board layout is designed to minimize coupling between

the two supplies to take advantage of the additional bypass

capacitance from each respective supply to the ground plane.

This enhances the performance when split input/output supplies

are used. If the input and output supplies are connected

together for single-supply operation (VCCI = VCCO), then

coupling between the two supplies is unavoidable; however,

careful board placement can help keep output return currents

away from the inputs.

LVDS-COMPATIBLE OUTPUT STAGE

Specified propagation delay dispersion performance is only

achieved by keeping parasitic capacitive loads at or below the

specified minimums. The outputs of the ADCMP604 and

ADCMP605 are designed to directly drive any standard LVDS-

compatible input.

USING/DISABLING THE LATCH FEATURE

The latch input is designed for maximum versatility. It can

safely be left floating or it can be driven low by any standard

TTL/CMOS device as a high speed latch. In addition, the pin

can be operated as a hysteresis control pin with a bias voltage of

1.25 V nominal and an input resistance of approximately

7000 Ω. This allows the comparator hysteresis to be easily

controlled by either a resistor or an inexpensive CMOS DAC.

Driving this pin high or floating the pin disables all hysteresis.

Hysteresis control and latch mode can be used together if an

open drain, an open collector, or a three-state driver is connected in

parallel to the hysteresis control resistor or current source.

Due to the programmable hysteresis feature, the logic threshold

of the latch pin is approximately 1.1 V regardless of VCC.

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout

techniques are essential for obtaining the specified performance.

Stray capacitance, inductance, inductive power and ground

impedances, or other layout issues can severely limit performance

and often cause oscillation. Large discontinuities along input

and output transmission lines can also limit the specified pulse-

width dispersion performance. The source impedance should

be minimized as much as is practicable. High source impedance,

in combination with the parasitic input capacitance of the

comparator, causes an undesirable degradation in bandwidth at

the input, thus degrading the overall response. Thermal noise

from large resistances can easily cause extra jitter with slowly

slewing input signals. Higher impedances encourage undesired

coupling.

COMPARATOR PROPAGATION DELAY

DISPERSION

The ADCMP604/ADCMP605 comparators are designed to

reduce propagation delay dispersion over a wide input overdrive

range of 5 mV to VCCI − 1 V. Propagation delay dispersion is the

variation in propagation delay that results from a change in the

degree of overdrive or slew rate (how far or how fast the input

signal is driven past the switching threshold).

Propagation delay dispersion is a specification that becomes

important in high speed, time-critical applications, such as data

communication, automatic test and measurement, and instru-

mentation. It is also important in event-driven applications, such

as pulse spectroscopy, nuclear instrumentation, and medical

imaging. Dispersion is defined as the variation in propagation

delay as the input overdrive conditions are changed (Figure 17

and Figure 18).

Rev. 0 | Page 10 of 16

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