CAT6611 데이터 시트보기 (PDF) - Unspecified
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CAT6611 Datasheet PDF : 29 Pages
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CAT6611
keeping the selected input-output format combination and the corresponding video processing block
selection. Please refer to the CAT6611 Programming Guide for suggested register setting.
PCLK
DE
H/VSYNC
D[23:0]
H/VSYNC
Clock
Embedded
Ctrl. Signals
Extraction
DE
Generator
H/VSYNC
DE
DE
Data
YCbCr422
to
YCbCr444
(upsampler)
YCbCr
RGB
(CSC)
Dithering
12-to-8
YCbCr444
to
YCbCr422
(downsampler)
HDCP
TMDS
Driver
TX2
TX1
TX0
TXC
Figure 3. Video data processing flow of CAT6611
Designated as D[23:0], the input video data could take on bus width of 8 bits to 24 bits. This input
interface could be configured through register setting to provide various data formats as listed in Table
1.
Although not explicitly depicted in Figure 3, input video clock (PCLK) can be configured to be
multiplied by 0.5, 2 or 4, so as to support special formats such as CCIR-656 and pixel-repeating. This
is also enabled by software programming.
General description of block functions is as follows:
Extraction of embedded control signals (Embedded Ctrl. Signals Extraction)
Input video formats with only embedded sync signals rely on this block to derive the proper Hsync,
Vsync and DE signals. Specifically, CCIR-656 video streams includes Start of Active Video (SAV) and
End of Active Video (EAV) that this block uses to extract the required control signals.
Generation of data enable signal (DE Generator)
DE signal defines the region of active video data. In cases where the video decoders supply no such
DE signals to CAT6611, this block is used to generate appropriate DE signal from Hsync, Vsync and
Clock.
Upsampling (YCbCr422 to YCbCr444)
In cases where input signals are in YCbCr 4:2:2 format and output is selected as 4:4:4, this block is
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2007 Chip Advanced Technology Inc. – All Right Reserved.
June-2007 Rev:1.0a 8/29
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