EP1C3Q104I6 데이터 시트보기 (PDF) - Altera Corporation

부품명

상세내역

제조사

EP1C3Q104I6

Cyclone FPGA Family

Altera Corporation 

Cyclone Device Handbook, Volume 1

Features

The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase

shifting

■ Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including

Altera® MegaCore® functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions.

Table 1–1. Cyclone Device Features

Feature

LEs

M4K RAM blocks (128 × 36 bits)

Total RAM bits

PLLs

Maximum user I/O pins (1)

EP1C3

2,910

13

59,904

1

104

Note to Table 1–1:

(1) This parameter includes global clock pins.

EP1C4

4,000

17

78,336

2

301

EP1C6

5,980

20

92,160

2

185

EP1C12

12,060

52

239,616

2

249

EP1C20

20,060

64

294,912

2

301

1–2

Preliminary

Altera Corporation

January 2007

Share Link: