MAX16025 데이터 시트보기 (PDF) - Unspecified

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MAX16025

Dual-/Triple-/Quad-Voltage, Capacitor Adjustable, Sequencing/Supervisory Circuits

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Dual-/Triple-/Quad-Voltage, Capacitor-

Adjustable, Sequencing/Supervisory Circuits

Calculate the reset timeout period as follows:

tRP

=

VTH−RESET

ICH−RESET

× CCRESET

+ 35 ×10−6

where VTH-RESET is 0.5V, ICH-RESET is 0.5µA, tRP is in

seconds, and CCRESET is in Farads. To ensure timing

accuracy and proper operation, minimize leakage at

CCRESET.

Adjustable Delay (CDLY_)

When VIN rises above VTH with EN_ high, the internal

250nA current source begins charging an external

capacitor connected from CDLY_ to GND. When the

voltage at CDLY_ reaches 1V, OUT_ goes high. When

OUT_ goes high, CDLY_ is immediately held low.

Adjust the delay (tDELAY) from when VIN rises above

VTH (with EN_ high) to OUT_ going high according to

the equation:

tDELAY

=

VTH−CDLY

ICH−CDLY

× CCDLY

+ 35 × 10−6

where VTH-CDLY is 1V, ICH-CDLY is 0.25µA, CCDLY is in

Farads, tDELAY is in seconds, and tDELAY+ is the inter-

nal propagation delay of the device. To ensure timing

accuracy and proper operation, minimize leakage

at CDLY.

Manual-Reset Input (MR)

Many µP-based products require manual-reset capabil-

ity, allowing the operator, a test technician, or external

logic circuitry to initiate a reset. A logic-low on MR

asserts RESET low. RESET remains asserted while MR

is low and during the reset timeout period (140ms fixed

or capacitor adjustable) after MR returns high. The MR

input has a 500nA internal pullup, so it can be left

unconnected, if not used. MR can be driven with TTL or

CMOS logic levels, or with open-drain/collector outputs.

Connect a normally open momentary switch from MR to

GND to create a manual-reset function. External

debounce circuitry is not required. If MR is driven from

long cables or if the device is used in a noisy environ-

ment, connect a 0.1µF capacitor from MR to GND to

provide additional noise immunity.

Pullup Resistor Values

The exact value of the pullup resistors for the open-

drain outputs is not critical, but some consideration

should be made to ensure the proper logic levels

when the device is sinking current. For example, if

VCC = 2.25V and the pullup voltage is 28V, keep the

sink current less than 0.5mA as shown in the Electrical

Characteristics table. As a result, the pullup resistor

should be greater than 56kΩ. For a 12V pullup, the

resistor should be larger than 24kΩ. Note that the ability

to sink current is dependent on the VCC supply voltage.

Power-Supply Bypassing

The device operates with a VCC supply voltage from

2.2V to 28V. When VCC falls below the UVLO threshold,

all the outputs go low and stay low until VCC falls below

1.2V. For noisy systems or fast rising transients on VCC,

connect a 0.1µF ceramic capacitor from VCC to GND

as close to the device as possible to provide better

noise and transient immunity.

Ensuring Valid Output with VCC Down to

0V (MAX16026/MAX16028/MAX16030 Only)

When VCC falls below 1.2V, the ability for the output to

sink current decreases. In order to ensure a valid out-

put as VCC falls to 0V, connect a 100kΩ resistor from

OUT/RESET to GND.

Typical Application Circuits

Figures 4 and 5 show typical applications for the

MAX16025–MAX16030. In high-power applications,

using an n-channel device reduces the loss across the

MOSFETs as it offers a lower drain-to-source on-resis-

tance. However, an n-channel MOSFET requires a suffi-

cient VGS voltage to fully enhance it for a low RDS_ON.

The application in Figure 4 shows the MAX16027 con-

figured in a multiple-output sequencing application.

Figure 5 shows the MAX16029 in a power-supply

sequencing application using n-channel MOSFETs.

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