2026AIVZ(2008) 데이터 시트보기 (PDF) - Intersil

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2026AIVZ
(Rev.:2008)

Real Time Clock/Calendar with I2C Bus™ and EEPROM

Intersil 

ISL12026, ISL12026A

AC Electrical Specifications (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 12)

MAX

TYP (Note 12) UNITS NOTES

tSU:STO STOP Condition Set-up Time

From SCL rising edge crossing 70%

600

of VDD, to SDA rising edge crossing

30% of VDD.

tHD:STO STOP Condition Hold Time for

From SDA rising edge to SCL falling

600

Read or Volatile Only Write

edge. Both crossing 70% of VDD.

tDH

Output Data Hold Time

From SCL falling edge crossing 30%

0

of VDD, until SDA enters the 30% to

70% of VDD window.

Cpin SDA and SCL Pin Capacitance

ns

ns

ns

10

pF

13

tWC Non-volatile Write Cycle Time

tR

SDA and SCL Rise Time

From 30% to 70% of VDD

tF

SDA and SCL Fall Time

From 70% to 30% of VDD

Cb

Capacitive Loading of SDA or SCL Total on-chip and off-chip

12

20

ms

10

20 + 0.1xCb

300

ns

11, 13

20 +0.1xCb

300

ns

11, 13

10

400

pF

11, 13

RPU SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.

1

Off-chip

For Cb = 400pF, max is about

2kΩ~2.5kΩ.

For Cb = 40pF, max is about

15kΩ~20kΩ

kΩ

11, 13

NOTES:

3. IRQ/FOUT Inactive.

4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz

5. VDD > VBAT +VBATHYS

6. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT ≥1.8V

7. Specified at +25°C.

8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.

9. Parameter is not 100% tested.

10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write

sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.

11. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.

12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

13. Limits should be considered typical and are not production tested.

Timing Diagrams

Bus Timing

tF

tHIGH

tLOW

tR

tHD:STO

SCL

tSU:STA

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

tSU:DAT

tHD:STA

tHD:DAT

tAA

tDH

tSU:STO

tBUF

5

FN8231.8

October 28, 2008

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