RTL8198-GR 데이터 시트보기 (PDF) - Realtek Semiconductor

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RTL8198-GR

IEEE 802.11n GIGABIT ETHERNET AP/ROUTER NETWORK PROCESSOR

Realtek Semiconductor 

RTL8198

Datasheet

Table of Contents

1. GENERAL DESCRIPTION ..............................................................................................................................................1

2. FEATURES .........................................................................................................................................................................3

3. BLOCK DIAGRAM ...........................................................................................................................................................5

4. PIN ASSIGNMENTS .........................................................................................................................................................6

4.1. PACKAGE IDENTIFICATION...........................................................................................................................................6

5. PIN DESCRIPTIONS.........................................................................................................................................................7

5.1. CONFIGURATION UPON POWER ON STRAPPING .........................................................................................................14

5.2. GMAC PIN MODE DESCRIPTION ...............................................................................................................................15

5.2.1. MAC Interface MII/GMII/RGMII Mode Pin Sharing Mappings ..........................................................................15

5.2.2. GMII/RGMII Interface Pin Descriptions..............................................................................................................15

5.2.3. MII MAC Mode Interface Pin Descriptions .........................................................................................................16

5.2.4. MII PHY Mode Interface Pin Descriptions ..........................................................................................................16

5.3. SHARED I/O PIN MAPPING .........................................................................................................................................17

6. MEMORY CONTROLLER ............................................................................................................................................19

6.1. SDR DRAM CONTROL INTERFACE ...........................................................................................................................19

6.1.1. Features................................................................................................................................................................19

6.1.2. Bank2 and Bank3..................................................................................................................................................19

6.2. DDR DRAM CONTROLLER .......................................................................................................................................20

6.2.1. Features................................................................................................................................................................20

6.3. SPI FLASH CONTROLLER ...........................................................................................................................................20

6.3.1. Features................................................................................................................................................................20

6.3.2. Pin Mode and Definition of Serial and Dual I/O..................................................................................................20

6.4. SOFTWARE REGISTER DEFINITIONS ...........................................................................................................................21

6.4.1. Memory Control Register (MCR) (0xB800_1000) ...............................................................................................21

6.4.2. DRAM Configuration Register (DCR) (0xB800_1004)........................................................................................22

6.4.3. DRAM Timing Register (DTR) (0xB800_1008)....................................................................................................23

6.4.4. DDR DRAM Calibration Register (DDCR) (0xB800_1050)................................................................................24

6.4.5. SPI Flash Configuration Register (SFCR) (0xB800_1200)..................................................................................25

6.4.6. SPI Flash Configuration Register 2 (SFCR2) (0xB800_1204).............................................................................25

6.4.7. SPI Flash Control & Status Register (SFCSR) (0xB800_1208) ...........................................................................26

6.4.8. SPI Flash Data Register (SFDR) (0xB800_120C) ...............................................................................................27

6.4.9. SPI Flash Data Register 2 (SFDR2) (0xB800_1210)...........................................................................................27

7. PERIPHERAL AND MISC CONTROL ........................................................................................................................28

7.1. GPIO CONTROL .........................................................................................................................................................28

7.1.1. GPIO Register Set (0xB800_3500).......................................................................................................................28

7.1.2. GPIO Port A, B, C, D Control Register (PABCD_CNR) (0xB800_3500)............................................................28

7.1.3. GPIO Port A, B, C, D Direction Register (PABCD_DIR) (0xB800-3508)...........................................................29

7.1.4. Port A, B, C, D Data Register (PABCD_DAT) (0xB800_350C) ..........................................................................29

7.1.5. Port A, B, C, D Interrupt Status Register (PABCD_ISR) (0xB800_3510) ...........................................................29

7.1.6. Port A, B Interrupt Mask Register (PAB_IMR) (0xB800_3514) ..........................................................................30

7.1.7. Port C, D Interrupt Mask Register (PCD_IMR) (0xB800_3518).........................................................................30

7.1.8. GPIO Port E, F, G, H Control Register (PEFGH_CNR) (0xB800_351C)...........................................................31

7.1.9. GPIO Port E, F, G, H Direction Register (PEFGH_DIR) (0xB800_3524) .........................................................31

7.1.10. Port E, F, G, H Data Register (PEFGH_DAT) (0xB800_3528)......................................................................32

7.1.11. Port E, F, G, H Interrupt Status Register (PEFGH_ISR) (0xB800-352C) ......................................................32

IEEE 802.11n Gigabit Ethernet AP/Router Network Processor

iii

Track ID: JATR-2265-11 Rev. 0.91

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