RTL8198-GR 데이터 시트보기 (PDF) - Realtek Semiconductor

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RTL8198-GR

IEEE 802.11n GIGABIT ETHERNET AP/ROUTER NETWORK PROCESSOR

Realtek Semiconductor 

RTL8198

Datasheet

List of Tables

TABLE 1. PIN DESCRIPTIONS .......................................................................................................................................................7

TABLE 2. CONFIGURATION UPON POWER ON STRAPPING .........................................................................................................14

TABLE 3. MAC INTERFACE MII/RGMII MODE PIN SHARING MAPPINGS .................................................................................15

TABLE 4. GMII/RGMII INTERFACE PIN DESCRIPTIONS ............................................................................................................15

TABLE 5. MII MAC MODE INTERFACE PIN DESCRIPTIONS .......................................................................................................16

TABLE 6. MII PHY MODE INTERFACE PIN DESCRIPTIONS ........................................................................................................16

TABLE 7. SHARED I/O PIN MAPPING .........................................................................................................................................17

TABLE 8. MEMORY CONTROL REGISTER (MCR) (0XB800_1000) ............................................................................................21

TABLE 9. DRAM CONFIGURATION REGISTER (DCR) (0XB800_1004).....................................................................................22

TABLE 10. DRAM TIMING REGISTER (DTR) (0XB800_1008) ...................................................................................................23

TABLE 11. DDR DRAM CALIBRATION REGISTER (DDCR) (0XB800_1050) .............................................................................24

TABLE 12. SPI FLASH CONFIGURATION REGISTER (SFCR) (0XB800_1200)..............................................................................25

TABLE 13. SPI FLASH CONFIGURATION REGISTER 2 (SPCR2) (0XB800_1204) .........................................................................25

TABLE 14. SPI FLASH CONTROL & STATUS REGISTER (SFCSR) (0XB800_1208) .....................................................................26

TABLE 15. SPI FLASH DATA REGISTER (SFDR) (0XB800_120C) ..............................................................................................27

TABLE 16. SPI FLASH DATA REGISTER 2 (SFDR2) (0XB800_1210) ..........................................................................................27

TABLE 17. GPIO REGISTER SET (0XB800_3500) .......................................................................................................................28

TABLE 18. GPIO PORT A, B, C, D CONTROL REGISTER (PABCD_CNR) (0XB800_3500) ........................................................28

TABLE 19. GPIO PORT A, B, C, D DIRECTION REGISTER (PABCD_DIR) (0XB800_3508)........................................................29

TABLE 20. PORT A, B, C, D DATA REGISTER (PABCD_DAT) (0XB800_350C)........................................................................29

TABLE 21. PORT A, B, C, D INTERRUPT STATUS REGISTER (PABCD_ISR) (0XB800_3510) .....................................................29

TABLE 22. PORT A, B INTERRUPT MASK REGISTER (PAB_IMR) (0XB800_3514).....................................................................30

TABLE 23. PORT C, D INTERRUPT MASK REGISTER (PCD_IMR) (0XB800_3518).....................................................................30

TABLE 24. GPIO PORT E, F, G, H CONTROL REGISTER (PEFGH_CNR) (0XB800_351C) .........................................................31

TABLE 25. GPIO PORT E, F, G, H DIRECTION REGISTER (PEFGH_DIR) (0XB800_3524).........................................................31

TABLE 26. PORT E, F, G, H DATA REGISTER (PEFGH_DAT) (0XB800_3528)..........................................................................32

TABLE 27. PORT E, F, G, H INTERRUPT STATUS REGISTER (PEFGH_ISR) (0XB800_352C)......................................................32

TABLE 28. PORT E, F INTERRUPT MASK REGISTER (PEF_IMR) (0XB800_3530).......................................................................32

TABLE 29. PORT G, H INTERRUPT MASK REGISTER (PGH_IMR) (0XB800_3534) ....................................................................33

TABLE 30. SHARED PIN REGISTER (PIN_MUX_SEL,0XB800_0040~0XB800_0043H).............................................................34

TABLE 31. SHARED PIN REGISTER (PIN_MUX_SEL_2,0XB800_0044~0XB800_0047H) .........................................................35

TABLE 32. NFBI FRAME FORMAT ..............................................................................................................................................39

TABLE 33. NFBI REGISTER ADDRESS MAPPING.........................................................................................................................39

TABLE 34. PHY IDENTIFIER REGISTER 1 (REGAD 0X02) ..........................................................................................................40

TABLE 35. PHY IDENTIFIER REGISTER 2 (REGAD 0X03) ..........................................................................................................40

TABLE 36. COMMAND REGISTER (REGAD 0X10)......................................................................................................................40

TABLE 37. ADDRESS REGISTER (HIGH) (REGAD 0X11) ............................................................................................................41

TABLE 38. ADDRESS REGISTER (LOW) (REGAD 0X12) .............................................................................................................41

TABLE 39. DATA REGISTER (HIGH) (REGAD 0X13) ..................................................................................................................42

TABLE 40. DATA REGISTER (LOW) (REGAD 0X14)...................................................................................................................42

TABLE 41. SEND COMMAND REGISTER (REGAD 0X15) ............................................................................................................42

TABLE 42. RECEIVE STATUS REGISTER (REGAD 0X16) ............................................................................................................42

TABLE 43. SYSTEM STATUS REGISTER (REGAD 0X17) .............................................................................................................43

TABLE 44. INTERRUPT MASK REGISTER (REGAD 0X19) ...........................................................................................................43

TABLE 45. INTERRUPT STATUS REGISTER (REGAD 0X1A)........................................................................................................44

TABLE 46. CPU INTERNAL REGISTER TABLE (0XB801_9000) ...................................................................................................45

TABLE 47. RTL8198 CPU RECEIVE COMMAND REGISTER (0XB801_9000) ..............................................................................45

TABLE 48. RTL8198 CPU SEND STATUS REGISTER (0XB801_9004) .........................................................................................45

TABLE 49. RTL8198 NFBI INTERRUPT MASK REGISTER (0XB801_9010).................................................................................46

TABLE 50. RTL8198 NFBI INTERRUPT STATUS REGISTER (0XB801_9014) ..............................................................................46

TABLE 51. OPERATING CONDITIONS...........................................................................................................................................47

TABLE 52. TOTAL POWER CONSUMPTION...................................................................................................................................47

IEEE 802.11n Gigabit Ethernet AP/Router Network Processor

vi

Track ID: JATR-2265-11 Rev. 0.91

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