RTL8198-GR 데이터 시트보기 (PDF) - Realtek Semiconductor

부품명

상세내역

제조사

RTL8198-GR

IEEE 802.11n GIGABIT ETHERNET AP/ROUTER NETWORK PROCESSOR

Realtek Semiconductor 

RTL8198

Datasheet

List of Figures

FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................5

FIGURE 2. PIN ASSIGNMENTS ......................................................................................................................................................6

FIGURE 3. NFBI (NON-FLASH BOOTING INTERFACE) ...............................................................................................................38

FIGURE 4. TYPICAL CONNECTION TO A CRYSTAL .....................................................................................................................53

FIGURE 5. TYPICAL CONNECTION TO AN OSCILLATOR..............................................................................................................53

FIGURE 6. SDR DRAM CLOCK SPECIFICATIONS-1 ...................................................................................................................54

FIGURE 7. SDR DRAM CLOCK SPECIFICATIONS-2 ...................................................................................................................54

FIGURE 8. MII CLOCK SPECIFICATIONS-1 .................................................................................................................................55

FIGURE 9. MII CLOCK SPECIFICATIONS-2 .................................................................................................................................55

FIGURE 10. GMII CLOCK SPECIFICATIONS-1 ..............................................................................................................................56

FIGURE 11. GMII CLOCK SPECIFICATIONS-2 ..............................................................................................................................56

FIGURE 12. RGMII CLOCK SPECIFICATIONS-1 ...........................................................................................................................57

FIGURE 13. RGMII CLOCK SPECIFICATIONS-2 ...........................................................................................................................57

FIGURE 14. SDR DRAM INPUT TIMING .....................................................................................................................................58

FIGURE 15. SDR DRAM OUTPUT TIMING..................................................................................................................................58

FIGURE 16. SDR DRAM ACCESS CONTROL TIMING ..................................................................................................................59

FIGURE 17. DDR DRAM ACCESS CONTROL TIMING .................................................................................................................61

FIGURE 18. SERIAL FLASH INTERFACE OUTPUT TIMING.............................................................................................................62

FIGURE 19. SERIAL FLASH INTERFACE INTPUT TIMING ..............................................................................................................62

FIGURE 20. MII OUTPUT TIMING ................................................................................................................................................63

FIGURE 21. MII INPUT TIMING ...................................................................................................................................................64

FIGURE 22. GMII TIMING CHARACTERISTICS.............................................................................................................................65

FIGURE 23. RGMII TIMING CHARACTERISTICS ..........................................................................................................................66

FIGURE 24. BOUNDARY-SCAN GENERAL TIMING .......................................................................................................................67

FIGURE 25. BOUNDARY-SCAN RESET TIMING ............................................................................................................................67

FIGURE 26. POWER UP SEQUENCE TIMING DIAGRAM.................................................................................................................68

FIGURE 27. POWER UP CONFIGURATION TIMING DIAGRAM .......................................................................................................68

FIGURE 28. SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING ................................................72

FIGURE 29. SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT..........................................................................72

FIGURE 30. SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING .......................................................72

FIGURE 31. DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD...................................................................73

FIGURE 32. DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME...........................................................................73

FIGURE 33. DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK ...........................................................................................73

FIGURE 34. REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING.........................................................................74

IEEE 802.11n Gigabit Ethernet AP/Router Network Processor

viii

Track ID: JATR-2265-11 Rev. 0.91

Share Link: