KE5BLME008 데이터 시트보기 (PDF) - KAWASAKI MICROELECTRONICS

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KE5BLME008

Longest Match Engine

KAWASAKI MICROELECTRONICS 

Kawasaki LSI

8K Longest Match Search Engine (KE5BLME008)

PRELIMINARY

Pin Name

ADD<3:0>

DAT<15:0>

CEN

RWN

FLN

AMFLN

Attribute

CPU Port Address

Input

LVTTL

CPU Port Data Bus

Input

LVTTL

CPU Port Enable

Input

LVTTL

Read/Write

Input

LVTTL

Full

Output

LVTTL

Almost Full

Output

LVTTL

DADD <9:0> DRAM Address

Output

LVTTL

DDAT <15:0> DRAM Data

Input/Output

LVTTL

DWEN

DRAM Write Enable

Output

LVTTL

DRAS

DRAM RAS

Output

LVTTL

DCAS

DRAM CAS

Output

LVTTL

DRI

RAS Timing Input

Input

LVTTL

VDD

Supply

GND

Ground

Description

ADD<3:0> is a register address.

# of Pins

4

DAT<15:0> is an input/output data bus 16

for a CPU port.

CEN serves as the CPU port access; CEN 1

Low enables the input operations of data

and command.

RWN determines the direction of the CPU 1

bus; RWN Low selects “write” cycle, and

RWN High “read” cycle.

FLN outputs Low when all entries are 1

filled with valid data.

AMFLN outputs Low when reaching

1

“almost full”; the number of entries is

equal to or exceeds the value stored in the

Almost Full Register.

DADD outputs DRAM address. Ensure 10

that it is connected to the DRAM address

pins.

DDAT <15:0> is a bi-directional data bus 16

to DRAM. Ensure that it is connected to

the DRAM data input/output.

DWEN is a DRAM Write Enable signal. 1

Ensure that it is connected to the DRAM

Write enable input.

DRAS is a row address select signal to the 1

DRAM. Ensure that it is connected to the

RAS pin of DRAM.

DCAS is a column address select signal to 1

the DRAM. Ensure that it is connected to

the relevant CAS pin of DRAM.

RAS Timing Input controls DRAM

1

timing. Ensure that it is connected to the

DRAS pin.

The voltage required is 3.3V.

21

Ground pin.

38

Version1.0.1

Proprietary and Confidential

7

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