KE5BLME064 데이터 시트보기 (PDF) - KAWASAKI MICROELECTRONICS

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KE5BLME064

Longest Match Engine

KAWASAKI MICROELECTRONICS 

Kawasaki LSI

64K Longest Match Search Engine (KE5BLME064)

PRELIMINARY

Pin Name Attribute

Description

#of

Pins

CEN

CPU Port Enable

CEN serves as the CPU port access; CEN

1

Input

Low enables the input operations of data

LVTTL

and command.

RWN Read/Write

RWN determines the direction of the CPU

1

Input

bus; RWN Low selects “write” cycle,

LVTTL

and RWN High “read” cycle.

FLN

Full

FLN outputs Low when all entries are

1

Output

filled with valid data.

LVTTL

AMFLN Almost Full

AMFLN outputs Low when reaching

1

Output

“almost full”; the number of entries is

LVTTL

equal to or exceeds the value stored in

the Almost Full Register.

MADD1 SRAM1 Address

MADD1 is SRAM1 address output.

16

<15:0> Output

Ensure that it is connected to SRAM1

LVTTL

address pins.

MDAT1 SRAM1 Data Bus

MDAT1 is a bi-directional Bus for

32

<31:0> Input/Output

SRAM1. Ensure that it is connected to

LVTTL

SRAM1 data pins.

MCS1N SRAM1 Chip Enable

MCS1N is SRAM1 chip enable signal.

1

Output

Ensure that it is connected to SRAM1

LVTTL

chip enable.

MOE1N SRAM1 Output Enable

MOE1N is SRAM1 Output Enable signal.

1

Output

Ensure that it is connected to SRAM1

LVTTL

output enable input.

MBWE1N SRAM1 Byte Write Enable

MBWE1N is SRAM1 Byte Write Enable

1

Output

signal. Ensure that it is connected to

LVTTL

SRAM1 Byte write enable input.

MBWA1N SRAM1 Synchronous Byte Write Enable MBWA1N is SRAM1 Synchronous Byte Write 1

Output

Enable signal. Ensure that it is connected to

LVTTL

SRAM1 Synchronous Byte write enable A input.

MBWB1N SRAM1 Synchronous Byte Write Enable MBWB1N is SRAM1 Synchronous Byte Write 1

Output

Enable signal. Ensure that it is connected to

LVTTL

SRAM1 Synchronous Byte write enable B input.

MBWC1N SRAM1 Synchronous Byte Write Enable MBWC1N is SRAM1 Synchronous Byte Write 1

Output

Enable signal. Ensure that it is connected to

LVTTL

SRAM1 Synchronous Byte write enable C input.

MBWD1N SRAM1 Synchronous Byte Write Enable MBWD1N is SRAM1 Synchronous Byte Write 1

Output

Enable signal. Ensure that it is connected to

LVTTL

SRAM1 Synchronous Byte write enable D input.

MADD2 SRAM2 Address

MADD2 is SRAM2 address output.

16

<15:0> Output

Ensure that it is connected to SRAM2

LVTTL

address pins.

MDAT2 SRAM2 Data Bus

MDAT2 is a bi-directional Bus for SRAM2.

32

<31:0> Input/Output

Ensure that it is connected to SRAM2

LVTTL

data pins.

MCS2N SRAM2 Chip Enable

MCS2N is SRAM2 chip enable signal.

1

Output

Ensure that it is connected to SRAM2

LVTTL

chip enable.

Version 2.5.4

Proprietary and Confidential

7

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