OZ990S 데이터 시트보기 (PDF) - O2Micro International
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OZ990S Datasheet PDF : 5 Pages
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PIN ASSIGNMENT
OZ990
SMBCLK
1
SMBDATA
2
PWRGD
3
MODE
4
PC[0] / GPIO[16]
5
PC[1] / GPIO[17]
6
PC[2] / GPIO[18]
7
PC[3] / GPIO[19]
8
GPIO[0] / SMIEVENT
9
GPIO[1] / WAKE
10
GPIO[2] / SMBALERT#
11
GPIO[3]
12
GPIO[4]
13
GND
14
28
VCC
27
32KHZ
26
RESETN
25
SRBTN # / GPIO[15]
24
GPIO[14]
23
GPIO[13]
22
GPIO[12]
21
GPIO[11]
20
GPIO[10]
19
GPIO[9]
18
GPIO[8]
17
SMBIDSEL[2] / GPO[7]
16
SMBIDSEL ]1] / GPO[6]
15
SMBIDSEL[0] / GPO [5]
PIN CONFIGURATION
Name
Pin No.
Type
Input
Drive
Definition
SMBCLK
1
I
TTL
-
SMBus Clock Input
SMBDATA
SMBus Clock Input for SMBus protocol communication.
2
I/O
TTL
12mA
SMBus Data Input/Output for SMBus protocol communication.
SMBus Data Input/Output
PWRGD
3
I
TTL
-
Host System Power Good
MODE
This pin indicates that the host system’s power, including the Core Logic chipsets, is stable. Before the host
system’s power is stable, this input pin will tri-state all the output pins from OZ990 with the exception of the
Power Control pins. The state of the PWRGD pin determines whether the OZ990 is in PMU or Alternate
PMU mode when RESETN is active. When pin MODE=1 and pin PWRGD=0, the OZ990 is in PMU mode.
When pin MODE=1 and pin PWRGD=1, the OZ990 is in Alternate PMU mode.
4
I
TTL
-
OZ990 Mode Input
PC[3:0]/
GPIO[19:16]
The OZ990 has 3 modes of operation: GPIO(with 20 GPIOs available), PMU(with 16 GPIOs available), and
Alternate PMU(with 16 GPIOs available). To use the OZ990 as a PMU, tie MODE pin to VDD and set
PWRGD LOW. For Alternate PMU mode, tie MODE pin to VDD and set PWRGD HIGH. For GPIO-only
mode, tie MODE pin LOW. Refer to MODE description for more details.
[8:5]
I/O
TTL
4mA
Power Control Outputs /
General Purpose I/Os
Pins PC[3:0]/GPIO[19:16] can be used as Power Control outputs for cold start, reset, Suspend, and Wakeup
or as regular GPIOs. Upon power up, if the OZ990 is in PMU mode, PC[3:0] will default to 0, with OZ990
initially in Suspend mode. By default, on a falling edge-triggered SRBTN#/GPIO[15] (with Wakeup function),
PC[3:0] will be set to 1 to power on the system. On a subsequent trigger of GPIO[15:8]’s Suspend and
Wakeup functions, the values in PC_SUSPEND[3:0] and PC_WAKE[3:0] in register 0Bh will be copied onto
the PC[3:0] output pins. Additionally, the OZ990 provides a power sequencing feature that allows up to 8
different programmable values of staggering time for the PC[3:0] outputs. PC[3:0] are also programmable
just like the GPIO[19:16] pins but with bits PCI[3:0] in register 0Bh as input data and PCO[3:0] in register
0Ch as output data values.
GPIO[0]/
9
SMIEVENT
I/O
TTL
4mA
General Purpose I/O /
SMIEVENT
Fully programmable GPIOs that can be used for a variety of dedicated or specific functions. Pin GPIO[0] has
SMIEVENT output as an alternate function. GPIO[0] defaults as outputs in PMU mode, and as input in
Alternate PMU and GPIO modes. It is also programmable to function as either GPI[0] input, GPO[0]output,
ALF[0] output, PWRON input, WAKE_DIS input, or ID[0] input(in Alternate PMU and GPIO modes). When
implementing as ID[0] input, GPIO[0]/SMIEVENT pin is internally latched from external pull-ups or pull-
downs, when RESETN is LOW. The values will be stored permanently in the ID Register and
GPIO[0]/SMIEVENT pin can then be reconfigured as an output. Refer to GPIO Config.1&2 Registers for
more details and GPIO Config. Tables for input/output selections.
OZ990-SF-1.6
Page 2
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