FDC37C93 데이터 시트보기 (PDF) - SMSC -> Microchip

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FDC37C93

Plug and Play Compatible Ultra I/O™ Controller with Soft Power Management

SMSC -> Microchip 

nPowerOn

Button_In

VTR

AB_DATA*

AB_CLK*

DATAIN*

DATAOUT*

CLK*, ENABLE*

nIOR

nIOW

AEN

SA[0:12] (nCS)

SA[13-15]

SD[O:7]

DRQ[0:3]

nDACK[0:3]

TC

IRQ[1,3-12,14,15]

RESET_DRV

IOCHRDY

SOFT

POWER

MANAGEMENT

ACCESS.bus

SERIAL

EEPROM

nSMI* IRQ13*

SMI

ACPI/SCI

POWER

MANAGEMENT

nGPA

nGPCS* nGPWR*

DECODER

DATA BUS

ADDRESS BUS

CONFIGURATION

REGISTERS

BIOS

BUFFER

nROMDIR

nROMCS

RD[0:7]

MULTI-MODE

PARALLEL

PORT/FDC

MUX

GENERAL

PURPOSE

I/O

16C550

COMPATIBLE

SERIAL

PORT 1

PD0-7

BUSY, SLCT, PE,

nERROR, nACK

nSTB, nSLCTIN,

nINIT, nALF

GP1[0:7]*

GP2[0:5]*

GP[4[0:7]*, GP5[0:1,3:4]*,

GP6[0:7]*, GP7[0:7]*

TXD1, nCTS1, nRTS1

RXD1

nDSR1, nDCD1, nRI1, nDTR1

CONTROL BUS

HOST

CPU

INTERFACE

Vcc Vss

WDATA

WCLOCK

SMSC

PROPRIETARY

82077

COMPATIBLE

VERTICAL

FLOPPYDISK

CONTROLLER

CORE

RCLOCK

DIGITAL

DATA

SEPARATOR

WITH WRITE

PRECOM-

PENSATION

RDATA

16C550

COMPATIBLE

SERIAL

PORT 2 WITH

INFRARED

IDE2

OPTIONAL

IDE

INTERFACE

CLOCK

GEN

nINDEX DENSEL nDS0,1

ICLOCK

(14.318)

nTRK0 nDIR nMTR0,1

nDSKCHG

nSTEP

nWDATA

DRVDEN0

nRDATA

nWRPRT nHDSEL DRVDEN1

nWGATE

MID0, MID1

HCLK

CLKO[1:3]

16CLK

(14.318)

*Multi-Function I/O Pin - Optional

8042

RTC

IRRX*, IRTX*

TXD2(IRTX), nCTS2, nRTS2

RXD2(IRRX)

nDSR2, nDCD2, nRI2, nDTR2

nHDCS2,3

IDE2_IRQ

IDE1_IRQ

nIDE1_OE

nIOWOP

nIOROP

nHDCS0, nHDCS1

KCLK

KDATA

MCLK

MDATA

P20*, P21*

P12*, P13*, P14*,P15*, P16*, P17*

XTAL1,2

VBAT

FDC37C93xAPM BLOCK DIAGRAM

14

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