FDC37C93 데이터 시트보기 (PDF) - SMSC -> Microchip

부품명

상세내역

제조사

FDC37C93

Plug and Play Compatible Ultra I/O™ Controller with Soft Power Management

SMSC -> Microchip 

FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

HOST PROCESSOR INTERFACE

The address map, shown below in Table 1,

shows the addresses of the different blocks of

the Super I/O immediately after power up. The

base addresses of the FDC, IDE, serial and

parallel ports, Bank 2 of the RTC registers,

auxiliary I/O and ACCESS.bus can be moved

via the configuration registers. Some addresses

are used to access more than one register.

The host processor communicates with the

FDC37C93xAPM through a series of read/write

registers. The port addresses for these registers

are shown in Table 1. Register access is

accomplished through programmed I/O or DMA

transfers. All registers are 8 bits wide except

the IDE data register at port 1F0H which is 16

bits wide. All host interface output buffers are

capable of sinking a minimum of 12 mA.

Table 1 - Super I/O Block Addresses

LOGICAL

ADDRESS

BLOCK NAME

DEVICE

NOTES

Base+(0-5) and +(7)

Floppy Disk

0

Base+(0-7)

Serial Port Com 1

4

Base+(0-7)

Serial Port Com 2

5

IR Support

Parallel Port

3

Base+(0-3)

SPP

Base+(0-7)

EPP

Base+(0-3), +(400-402)

ECP

Base+(0-7), +(400-402)

ECP+EPP+SPP

Base1+(0-7), Base2+(0)

IDE 1

1

Base1+(0-7), Base2+(0)

IDE 2

2

70, 71

RTC

6

Base2+(0,1)

60, 64

KYBD

7

Base1+(0)

Base2+(0)

Base+(0-3)

Aux. I/O

ACCESS.bus

8

GPR

GPW

9

Base1+(0-11)

ACPI

A

Base2+(0-7)

Note: Refer to the configuration register descriptions for setting the base address

15

Share Link: