VV5300 데이터 시트보기 (PDF) - Vision

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VV5300

Integrated CMOS Image Sensor with on-chip ADC.(Sensor)

Vision 

VV5300 Sensor

System Clock Generation

VV5300 generates a system clock when a quartz crystal or ceramic resonator circuit is connected to the CLKI

and CLKO pins. The device can also be driven directly from an external clock source driving CLKI.

VV5300

CLK

CLOCK

DIVISION

VV5300

CLK

CLOCK

DIVISION

CKIN

C1=C2=47pF

31

R1=1MΩ

R2=510Ω

X1= 14.318MHz (up to 60fps)

17.73MHz (up to 50fps)

C1

CKOUT

R1

32

R2

C2

X1

CKIN

31

Clock

Source

CMOS Driver

CKOUT

32

Camera Clock Source

For greater flexibility the input frequency can be divided by 2, 4, 8 or 16 to select the pixel clock frequency.

Two bits in the clock division register in the serial interface select the input clock frequency divisor. The table

below gives the different frame rates that can be selected, when CLKI = 14.318MHz, for each divisor. The

default clock divisor setting is a divide by 2. To achieve maximum frame rates data is converted at 4 bit

resolution.

CLKI

(MHz)

Divisor

Pixel Freq.

(kHz)

Frame rate1

(fps)

Comments

14.318

0

0

2

1790

59.98

default

14.318

0

1

4

895

29.99

14.318

1

0

8

448

15.01

14.318

1

1

16

224

7.5

Clock Division (60Hz Video Mode)

1.

Approximate frame rate. Assumes 160 x 120 image format, parallel data output and 4 bit data

conversion

cd34011-b.fm

17/10/97

10

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