MC33385DH/R2 데이터 시트보기 (PDF) - Freescale Semiconductor
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MC33385DH/R2 Datasheet PDF : 18 Pages
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ELECTRICAL CHARACTERISTICS
DYNAMIC CHARACTERISTIC
DYNAMIC CHARACTERISTIC
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 7.0 V ≤ VSUP ≤ 18 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INPUTS
Input Frequency (NON1 to NON4)
OUTPUTS TIMING
Positive Output Voltage Ramp (with inductive load)
VOUT = 4V... 16V
VOUT = 16V... Vclp
Negative Output Voltage Ramp (25%... 75%)
Internal Switch-on-Time Charge Pump
(NON = LOW... VGATE = 0.9 * VBAT)
Turn ON Delay
(NON = 50%, VOUT = 0.9 * VBAT)
Turn OFF Delay
(NON = 50%, VOUT = 0.1 * VBAT)
(NON = 50%, VOUT = 4V)
Undervoltage Protection
Max ON time after a output voltage ramp from
0V to 25V at VCC = 0V...VCCPRO
Matching Turn ON Delay
(NON = 50%, VOUT = 0.9 * VBAT)
Rise time Turn OFF
(10% - 90% of VCLP)
fIN
0.0
1000
Hz
OVRP1
2.0
3.0
OVRP2
3.5
6.0
OVRN
1.75
3.0
tDCP
tDON
1.0
2.5
5.0
V/µs
10
V/µs
4.0
V/µs
40
µs
5.0
µs
tDOFFA
tDOFFB
tRPON
1.0
3.0
µs
4.7
7.5
µs
100
µs
tMON
- 3.0
3.0
µs
tROFF
8.5
12
µs
DIAGNOSTIC
Short to GND Filter Time
TSCG
140
Open Load Filter Time
tOL
140
SERIAL DIAGNOSTIC LINK : LOAD CAPACITOR AT SDI AND SDO = 100PF
Clock Frequency (50% duty cycle)
Minimum Time CLK = HIGH
Minimum Time CLK = LOW
Propagation Delay (CLF Data at SDO valid)
NCS = LOW to Data at SDO Valid
CLK Low Before NCS Low
(Setup time CLK to NCS change High/Low)
fCLK
3.0
tCLH
100
tCLL
100
tPCLD
tPCLD
tSCLCH
100
CLK Change Low/High after NCS = Low
SDI Input Set up Time
(CLK change High/Low after SDI data valid)
tHCLCL
100
tSCLD
20
SDI Input Hold Time (SDI data hold after CLK change High/Low)
CLK Low Before NCS High
tHCLD
tSCLCL
150
250
µs
250
µs
MHz
ns
ns
100
ns
100
ns
ns
ns
ns
20
ns
ns
Analog Integrated Circuit Device Data
Freescale Semiconductor
33385
7
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