74LVC132A(2006) 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC132A Datasheet PDF : 15 Pages
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NXP Semiconductors
6. Pinning information
6.1 Pinning
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
74LVC132A
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
001aaf590
Fig 4. Pin configuration SO14 and TSSOP14
6.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
74LVC132A
Quad 2-input NAND Schmitt trigger
74LVC132A
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND(1)
13 4B
12 4A
11 4Y
10 3B
9 3A
001aaf591
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration DHVQFN14
74LVC132A_1
Product data sheet
Rev. 01 — 15 December 2006
© NXP B.V. 2006. All rights reserved.
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