74VHC123AMTCX(2007) 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74VHC123AMTCX Datasheet PDF : 14 Pages
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Functional Description
1. Stand-by State
The external capacitor (Cx) is fully charged to VCC in
the Stand-by State. That means, before triggering,
the QP and QN transistors which are connected to the
Rx/Cx node are in the off state. Two comparators that
relate to the timing of the output pulse, and two refer-
ence voltage supplies turn off. The total supply cur-
rent is only leakage current.
2. Trigger Operation
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling sig-
nal; and third, where the A input is LOW and the B
input is HIGH, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C1
and C2 start operating, and QN is turned on. The
external capacitor discharges through QN. The volt-
age level at the Rx/Cx node drops. If the Rx/Cx volt-
age level falls to the internal reference voltage VrefL,
the output of C1 becomes LOW. The flip-flop is then
reset and QN turns off. At that moment C1 stops but
C2 continues operating.
After QN turns off, the voltage at the Rx/ Cx node
starts rising at a rate determined by the time constant
of external capacitor Cx and resistor Rx.
Upon triggering, output Q becomes HIGH, following
some delay time of the internal F/F and gates. It stays
HIGH even if the voltage of Rx/Cx changes from fall-
ing to rising. When Rx/Cx reaches the internal refer-
ence voltage VrefH, the output of C2 becomes LOW,
the output Q goes LOW and C2 stops its operation.
That means, after triggering, when the voltage level
of the Rx/Cx node reaches VrefH, the IC returns to its
MONOSTABLE state.
With large values of Cx and Rx, and ignoring the dis-
charge time of the capacitor and internal delays of
the IC, the width of the output pulse, tW (OUT), is as
follows:
tW (OUT) = 1.0 Cx Rx
3. Retrigger operation (74VHC123A)
When a new trigger is applied to either input A or B
while in the MONOSTABLE state, it is effective only if
the IC is charging Cx. The voltage level of the Rx/Cx
node then falls to VrefL level again. Therefore the Q
output stays HIGH if the next trigger comes in before
the time period set by Cx and Rx.
If the new trigger is very close to a previous trigger,
such as an occurrence during the discharge cycle, it
will have no effect.
The minimum time for a trigger to be effective 2nd
trigger, tRR (Min), depends on VCC and Cx.
4. Reset Operation
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q
output is held LOW and the trigger control F/F is
reset. Also, Qp turns on and Cx is charged rapidly to
VCC.
This means if CLR is set LOW, the IC goes into a wait
state.
©1993 Fairchild Semiconductor Corporation
74VHC123A Rev. 1.2
5
www.fairchildsemi.com
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