29103BRA 데이터 시트보기 (PDF) - Intersil
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29103BRA Datasheet PDF : 8 Pages
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HM-65262
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention;
within VCC to VCC +0.3V.
2. On RAMs which have selects or output enables (e.g., S,
G), one of the selects or output enables should be held in
the deselected state to keep the RAM outputs high
impedance, minimizing power dissipation.
3. Inputs which are to be held high (e.g., E) must be kept
between VCC +0.3V and 70% of VCC during the power up
and down transitions.
4. The RAM can begin operation > 55ns after VCC reaches
VCC
E
4.5V
DATA RETENTION
MODE
VCC ≥ 2.0V
VCC -0.3V TO VCC +0.3V
4.5V
>55ns
FIGURE 5. DATA RETENTION TIMING
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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