ADJD-J823 데이터 시트보기 (PDF) - Avago Technologies
부품명
상세내역
제조사
ADJD-J823 Datasheet PDF : 18 Pages
| |||
Pin Information
PIN NAME
1 NC
2 PWMB
3 PWMG
4 PWMR
5 DGND
6 DGND
7 DVDD
8 AGND
9 CLKIO
10 XRST
TYPE
No connect
Output
Output
Output
Ground
Ground
Power
Ground
Output
Input
11 SCLSLV
12 SDASLV
Input
Input/Output
(tri-state high)
13 SCLPROM Output
14 SDAPROM Input/Output
(tri-state high)
15 SLEEP
Input
16 AGND
17 AGND
18 AGND
19 AVDD
20 NC
Ground
Ground
Ground
Power
No connect
DESCRIPTION
No connect. Leave floating.
PWMB is the active-high blue pulse width modulation output pin.
Tie it to the blue LED driver channel.
PWMG is the active-high green pulse width modulation output pin.
Tie it to the green LED driver channel.
PWMR is the active-high red pulse width modulation output pin.
Tie it to the red LED driver channel.
Tie to digital ground.
Tie to digital ground.
Digital power pin.
Tie to analog ground.
CLKIO outputs a reference internal clock signal.
Global, asynchronous, active low system reset.
When asserted low, XRST resets all registers.
Minimum reset pulse low is 10us and must be provided by external
circuitry.
SDASLV and SCLSLV are the serial interface communications pins.
SDASLV is the bidirectional data pin and SCLSLV is the interface clock.
A pull-up resistor should be tied to SDASLV because it goes tri-state to
output logic 1.
An external serial I2C EEPROM can be connected to the device to store
calibration and configuration data. SDAPROM and SCLPROM should be
tied to the I2C data (SDA) and clock (SCL) pins of the EEPROM. A pull-up
resistor should be tied to SDAPROM because it goes tri-state to output
logic 1.
When SLEEP=1, the device goes into sleep mode. In sleep mode, all
analog circuits are powered down and the clock signal is gated away from
the core logic resulting in very low current consumption.
Tie to analog ground.
Tie to analog ground.
Tie to analog ground.
Analog power pin.
No connect. Leave floating.
Share Link: 