ADP3203 데이터 시트보기 (PDF) - Analog Devices
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ADP3203 Datasheet PDF : 16 Pages
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Pin
Mnemonic
12
PWRGD
13
SD
14
CLAMP
15
DRVLSD
16
SS
17
COREFB
18
DACOUT
19
GND
20
OUT1
ADP3203
PIN FUNCTION DESCRIPTIONS (continued)
Function
Power Good (Active High). This open-drain output pin, via the assistance of an external pull-up
resistor to the desired voltage, indicates that the core voltage is within the specified tolerance of the
VID programmed value, or else is in a VID transition state as indicated by a recent state transition
of either the BOM or DPRSLP pins. PWRGD is deactivated (pulled low) when the IC is disabled,
in UVLO Mode, or starting up, or the COREFB voltage is out of the core Power Good window.
The open-drain output allows external wired ANDing (logical NORing) with other open-drain/
collector Power Good indicators.
Shutdown (Active Low). This is a digital input pin coming from a system signal that, in its active
state, shuts down the IC operation, placing the IC in its lowest quiescent current state for maximum
power savings.
Clamp (Active High). This open-drain output pin, via the assistance of an external pull-up
resistor, indicates that the core voltage should be clamped for its protection. To allow the highest
level of protection, the CLAMP signal is developed using both a redundant reference and a redun-
dant feedback path with respect to those of the main regulation loop. The signal is timed out using
the soft start capacitor, so an external current protection mechanism (e.g., a fuse or ac adapter’s
current limit) should be tripped within ~3 times the programmed soft start time (e.g., 5 ms~10 ms).
In a preferred and more conservative configuration, the core voltage is clamped by an external FET.
The initial protection function is served when it is activated by detection of either an overvoltage or
a reverse voltage condition on the COREFB pin. Due to loss of the latched signal at IC power-off,
backup protection function is served by connecting the pull-up resistor to a system “ALWAYS”
regulator output (e.g., V5_ALWAYS). If the external FET is used, this implementation will keep
the core voltage clamped until the ADP3203 has power reapplied, thus keeping protection for the
CPU even after a hard-failure power-down and restart (e.g., a shorted top or bottom FET).
Drive-Low Shutdown (Active Low). In its active state, this digital output pin indicates that the lower
FET of the core VR should be disabled. In the suggested application schematic, this pin is directly
connected to the pin of the same name on the ADP3415 or other driver IC. Drive-low shutdown is
normally activated by the DPRSLP signal corresponding to a light load condition, but a number of
dynamic conditions can override the control of this pin as needed.
Soft Start. The output of this analog I/O pin is a controlled current source used to charge or
discharge an external grounded capacitor; the input is the detected voltage that is indicative
of elapsed time. The pin controls the soft start time of the IC as well as the hiccup cycle time during
overload, including but not limited to short circuit, overvoltage, and reverse voltage. Hiccup
operation was added to reduce short circuit power dissipation by more than an order of magnitude,
while still allowing an automatic restart when the failure mode ceased.
Core Feedback. This high impedance analog input pin is used to monitor the output voltage for
setting the proper state of the PWRGD and CLAMP pins. It is generally recommended to RC-filter
the ripple and noise from the monitored core voltage, as suggested by the application schematic.
Digital-to-Analog Converter Output. This output voltage is the VID-controlled reference voltage
whose primary function is to determine the output voltage regulation point.
Ground
Output to Driver 1. This digital output pin is used to command the state of the switched node via
the driver and MOSFET switches. It should be connected to the IN pin of the ADP3415 driver that
corresponds to the first of two channels.
REV. 0
–7–
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