ADP3203 데이터 시트보기 (PDF) - Analog Devices

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ADP3203

2-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs

Analog Devices 

ADP3203

Pin

Mnemonic

21

OUT2

22

CS1

23

CS2

24

VCC

25

RAMP

26

REG

27

CS+

28

CS–

PIN FUNCTION DESCRIPTIONS (continued)

Function

Output to Driver 2. This digital output pin is used to command the state of the switched node via

the driver. It should be connected to the IN pin of the ADP3415 driver that corresponds to the

second of two channels.

Current Sense, Channel 1. This high impedance analog input pin is used to provide negative

feedback of the current information for the first of two channels.

Current Sense, Channel 2. This high impedance analog input pin is used to provide negative

feedback of the current information for the second of two channels. The pin is also used to deter-

mine whether the chip is acting as a single- or dual-phase controller. If the pin is tied to VCC but

not a sense resistor, then the dual-phase operation is disabled; the chip works as a single-phase controller.

In this condition, the second phase’s output signal (OUT2) does not switch but stays static low.

Power Supply. This should be connected to the system’s 3.3 V power supply output.

Regulation Ramp Feedback Input. The RAMP pin voltage is compared against the REG pin for

cycle-by-cycle switching response. Several switched current sources also appear at this input: the

cycle-by-cycle hysteresis setting switched current programmed by the HYSSET pin, the BOM shift

current programmed by the BSHIFT pin, and the Deep Sleep shift current programmed by the

DSHIFT pin. The external resistive termination at this pin sets the magnitude of the hysteresis

applied to the regulation loop.

Regulation Voltage Summing Input. This is a high impedance analog input pin into which the

voltage reference of the feedback loop allows the summing of both the DACOUT voltage and the

core voltage for programming the output resistance of the core voltage regulator. This is also the pin

at which an optimized transient response can be tailored using Analog Devices’ patented ADOPT

design technique.

Current Limit Positive Sense. This high impedance analog input pin is multiplexed between either

of the two current-sense inputs during the high state of the OUT pin of the respective channel.

During the common off-time of both channels, the pin’s voltage reflects the average of the two

channels. The multiplexed current sense signal is passed to the core comparator through an external

resistive termination connected from this pin to the RAMP pin. The external (RAMP) resistor sets

the magnitude of the hysteresis applied to the regulation loop.

Current Limit Negative Sense. This high impedance analog input pin is normally Kelvin

connected to the negative node of the current sense resistor(s) via a current-limit programming

resistor. A hysteretically controlled current—three times the current programmed at the HYSSET

pin—also flows out of this pin and develops a current-limit setting voltage across that resistor,

which must then be matched by the inductor current flowing in the current sensing resistor in order

to trigger the current limit function. When triggered, the current flowing out of this pin is reduced

to two-thirds of its previous value, producing hysteresis in the current limiting function.

–8–

REV. 0

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