AM27C010-120JC 데이터 시트보기 (PDF) - Advanced Micro Devices

부품명

상세내역

제조사

AM27C010-120JC

1 Megabit (128 K x 8-Bit) CMOS EPROM

Advanced Micro Devices 

FINAL

Am27C010

1 Megabit (131,072 x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

s Fast access time

— 45 ns maximum access time

s Low power consumption

— 20 µA typical CMOS standby current

s JEDEC-approved pinout

s Single +5 V power supply

s ±10% power supply tolerance available

s 100% Flashrite™ programming

— Typical programming time of 16 seconds

GENERAL DESCRIPTION

The Am27C010 is a 1 Megabit ultraviolet erasable pro-

grammable read-only memory. It is organized as 128K

words by 8 bits per word, operates from a single +5 V

supply, has a static standby mode, and features fast

single address location programming. Products are

available in windowed ceramic DIP packages as well

as plastic one time programmable (OTP) PDIP, TSOP,

and PLCC packages.

Typically, any byte can be accessed in less than 45 ns,

allowing high-performance microprocessors to oper-

ate without wait states. The Am27C010 offers sepa-

rate Output Enable (OE) and Chip Enable (CE)

s Latch-up protected to 100 mA from –1 V to

VCC + 1 V

s High noise immunity

s Versatile features for simple interfacing

— Both CMOS and TTL input/output compatibility

— Two line control functions

s Compact 32-pin DIP, PDIP, TSOP, PLCC

packages

controls, thus eliminating bus contention in a multiple

bus microprocessor system.

AMD’s CMOS process technology provides high

speed, low power, and high noise immunity. Typical

power consumption is only 100 mW in active mode,

and 100 µW in standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in

blocks, or at random. The Am27C010 supports AMD’s

Flashrite programming algorithm (100 µs pulses) re-

sulting in a typical programming time of 16 seconds.

BLOCK DIAGRAM

OE

CE

PGM

A0–A16

Address

Inputs

VCC

VSS

VPP

Output Enable

Chip Enable

and

Prog Logic

Y

Decoder

X

Decoder

Data Outputs

DQ0–DQ7

Output

Buffers

Y

Gating

1,048,576

Bit Cell

Matrix

10205F-1

Publication# 10205 Rev: F Amendment/+2

Issue Date: August 1997

Share Link: