AT25128-10PI-2.7 데이터 시트보기 (PDF) - Atmel Corporation

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AT25128-10PI-2.7

SPI Serial EEPROMs

Atmel Corporation 

AT25128/256

The AT25128/256 is capable of a 64-byte page write operation. After each byte of data

is received, the six-low order address bits are internally incremented by one; the high-

order bits of the address will remain constant. If more than 64 bytes of data are transmit-

ted, the address counter will roll over and the previously written data will be overwritten.

The AT25128/256 is automatically returned to the write disable state at the completion

of a write cycle.

NOTE: If the device is not Write enabled (WREN), the device will ignore the Write

instruction and will return to the standby state, when CS is brought high. A new CS fall-

ing edge is required to reinitiate the serial communication.

Table 10. Address Key

Address

AN

Don’t Care Bits

AT25128

A13 - A0

A15 - A14

AT25256

A14 - A0

A15

Timing Diagrams (for SPI Mode 0 (0, 0))

Figure 3. Synchronous Data Timing

CS

SCK

VIH

VIL

tCSS

VIH

VIL

VIH

SI

VIL

VOH

SO

VOL

HI-Z

tWH

tSU

tH

VALID IN

tWL

tV

tCS

tCSH

tHO

tDIS

HI-Z

9

0872O–SEEPR–03/05

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