ATC35 데이터 시트보기 (PDF) - Atmel Corporation

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ATC35

Cell-based ASIC

Atmel Corporation 

Compiled LROM

Megacells

ATC35 Summary

The LROM (Large ROM) compiler allows the system designer to acheive high-density

and low-power applications. Multi-block megacells with total capacity up to 4M-bits can

be generated by the LROM compiler.

Compiled memories are diffusion-programmed ROMs with a synchronous access proto-

col, as is for the ROM. The compiler expects a programming file: lrom<xyz>.prg that

contains the LROM pattern. If the .prg file is not available, a random contents is auto-

matically generated. Unlike the ROM compiler, only buffered outputs can be acheived

using the LROM compiler.

The range of permitted LROM configurations is as follows:

Total size:

64K...4M

Number of words: 2K...512K

Bits per word: 8, 16 or 32

Number of address bits:11...19

The memory is organized in multiple blocks of 64K bits each.

Number of blocks:

1...32

Number of rows per block: 256

Number of columns per block:256

I/O pins in compiled megacells are the following:

me input: Memory Enable.

add<i> inputs: Address.

do<i> outputs: buffered output data.

vdd and gnd: power and ground supplies.

The following table shows the performances for some LROM configurations. Access

time (tACC), cycle time (tCYC) and Dynamic Power dissipation refer to Max industrial

conditions.

Word Depth

Width (mm)

Height (mm)

Access Time (tACC) (nsec)

Cycle Time (tCYC) (nsec)

Dynamic Power (mW/MHz)

Word Size = 16

16K

0.979

0.858

11.37

14.15

0.26

32K

3.570

0.539

11.84

14.40

0.56

64K

1.863

1.716

12.53

15.30

0.75

128K

1.863

3.078

15.19

19.14

0.90

13

1063CS–CBIC–01/03

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