CS61318 데이터 시트보기 (PDF) - Cirrus Logic

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CS61318

E1 Line Interface Unit

Cirrus Logic 

CS61318

TRING, unless TAOS has been selected, in which

case AMI-encoded continuous ones are transmitted

at the TCLK frequency. The receiver RTIP and

RRING inputs are ignored when local loopback is

in effect.

2.8 Remote Loopback

Remote loopback is selected by setting RLOOP,

pin 26, high (CR1.5 = 1 in host mode). In remote

loopback, the recovered clock and data input on

RTIP and RRING are sent back out on the line via

TTIP and TRING. Selecting remote loopback over-

rides a TAOS request. The recovered clock and data

from the incoming signal are also sent to RCLK,

RPOS and RNEG (RDATA). Note: simultaneous se-

lection of local and remote loopback modes will cause

a device reset to occur (see Reset).

2.9 Network Loopback

Network Loopback (automatic remote loopback)

can be commanded from the network when the

Network Loopback detect function is enabled. In

Host Mode, Network Loopback (NLOOP) detec-

tion is enabled by writing ones to TAOS, LLOOP,

and RLOOP, then clearing these three bits on a suc-

cessive write cycle. In hardware mode, Network

Loopback can be enabled by tying RLOOP to

RCLK or by setting TAOS, LLOOP, and RLOOP

high for at least 200 ns, and then low. Once enabled

Network Loopback functionality will remain in ef-

fect until RLOOP is activated or the device is reset.

When NLOOP detection is enabled, the receiver

monitors the input data stream for the NLOOP data

patterns (00001 = enable, 001 = disable). When an

NLOOP enable data pattern is repeated for a mini-

mum of five seconds (with less than 10E-3 BER),

the device initiates a remote loopback. Once Net-

work Loopback detection is enabled and activated

by the NLOOP data pattern, the loopback is identi-

cal to Remote Loopback initiated at the device.

NLOOP is reset if the disable pattern (001) is re-

ceived for 5 seconds, or by activation of RLOOP.

NLOOP is temporarily suspended by LLOOP, but

the NLOOP state is not reset.

2.10 Alarm Indication Signal

The receiver sets the register bit, AIS, to “1” when

less than 9 zeros are detected out of 8192 bit peri-

ods. AIS returns to “0” upon the first read after the

AIS condition is removed, determined by 9 or more

zeros out of 8192 bit periods.

2.11 Serial Interface

In the Host Mode, pins 24 through 28 serve as a mi-

crocontroller interface. On-chip registers can be

written to via the SDI pin or read from via the SDO

pin at the clock rate determined by SCLK. Through

these registers, a host controller can be used to con-

trol operational characteristics and monitor device

status. The serial port read/write timing is indepen-

dent of the system transmit and receive timing.

Data transfers are initiated by taking the chip select

input, CS, low (CS must initially be high). Address

and input data bits are clocked in on the rising edge

of SCLK. The clock edge on which output data is

stable and valid is determined by CLKE as shown

in Table 1. Data transfers are terminated by setting

CS high. CS may go high no sooner than 50 ns after

the rising edge of the SCLK cycle corresponding to

the last write bit. For a serial data read, CS may go

high any time to terminate the output and set SDO

to high impedance.

Figure 9 shows the timing relationships for data

transfers when CLKE = 0. When CLKE = 1, data

bit D7 is held until the falling edge of the 16th clock

cycle. When CLKE = 0, data bit D7 is held valid

until the rising edge of the 17th clock cycle. SDO

goes high-impedance after CS goes high or at the

end of the hold period of data bit D7.

SDO goes to a high impedance state when not in

use. SDO and SDI may be tied together in applica-

tions where the host processor has a bi-directional

I/O port.

DS441PP2

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