CY7C1019B-12VI 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
제조사
CY7C1019B-12VI Datasheet PDF : 9 Pages
| |||
CY7C1019B/
CY7C10191B
AC Test Loads and Waveforms
R1 480Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 480Ω
5V
OUTPUT
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Characteristics[4] Over the Operating Range
7C10191B-10
7C1019B-12
7C1019B-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low Z
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
Write Cycle[7, 8]
10
12
15
ns
10
12
15
ns
3
3
3
ns
10
12
15
ns
5
6
7
ns
0
0
0
ns
5
6
7
ns
3
3
3
ns
5
6
7
ns
0
0
0
ns
10
12
15
ns
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tAW
Address Set-Up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Set-Up to Write End
5
6
8
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[5, 6]
0
0
0
ns
3
3
3
ns
5
6
7
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05026 Rev. *A
Page 3 of 9
Share Link: 