CY7C1049DV33(2006) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1049DV33 Datasheet PDF : 8 Pages
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CY7C1049DV33
AC Test Loads and Waveforms[5]
10 ns device
OUTPUT
Z = 50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50Ω
1.5V
(a)
High-Z characteristics:
3.3V
OUTPUT
5 pF
3.0V
30 pF* GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
R 317Ω
(b)
Fall Time: 1 V/ns
R2
351Ω
(c)
AC Switching Characteristics[6] Over the Operating Range
-10 (Industrial) -12 (Automotive)
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
tpower[7]
tRC
tAA
tOHA
VCC(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
100
100
µs
10
12
ns
10
12
ns
3
3
ns
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low-Z
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[9]
CE HIGH to High-Z[8, 9]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
Write Cycle[10, 11]
10
12
ns
5
6
ns
0
0
ns
5
6
ns
3
3
ns
5
6
ns
0
0
ns
10
12
ns
tWC
Write Cycle Time
10
12
ns
tSCE
CE LOW to Write End
7
8
ns
tAW
Address Set-up to Write End
7
8
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
7
8
ns
tSD
Data Set-up to Write End
5
6
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low-Z[9]
WE LOW to High-Z[8, 9]
0
0
ns
3
3
ns
5
6
ns
Notes:
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05475 Rev. *C
Page 3 of 8
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