CY7C68001(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C68001 Datasheet PDF : 42 Pages
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CY7C68001
3.6.3 Endpoint Configurations (High-speed Mode)
EP0 IN&OUT
64
64
Group A
512
EP2
512
512
EP4
512
512
512
EP2
512
512
64
EP2
1024
1024
Group B
512
EP6
512
512
EP8
512
512
512
EP6
512
512
EP6
1024
1024
64
64
Group C
512
EP2
512
512
512
1024
EP2
1024
EP6
512
512
512
EP8
512
1024
512
EP8
512
64
1024
EP2
1024
1024
1024
Figure 3-1. Endpoint Configuration
Endpoint 0 is the same for every configuration as it serves as
the CONTROL endpoint. For Endpoints 2, 4, 6, and 8, refer to
Figure 3-1. Endpoints 2, 4, 6, and 8 may be configured by
choosing either:
• One configuration from Group A and one from Group B
• One configuration from Group C.
Some example endpoint configurations are as follows.
• EP2: 1024 bytes double-buffered, EP6: 512 bytes quad-
buffered.
• EP2: 512 bytes double-buffered, EP4: 512 bytes double-
buffered, EP6: 512 bytes double-buffered, EP8: 512 bytes
double buffered.
• EP2: 1024 bytes quad-buffered.
3.6.4 Default Endpoint Memory Configuration
At power-on-reset, the endpoint memories are configured as
follows:
• EP2: Bulk OUT, 512 bytes/packet, 2x buffered.
• EP4: Bulk OUT, 512 bytes/packet, 2x buffered.
• EP6: Bulk IN, 512 bytes/packet, 2x buffered.
• EP8: Bulk IN, 512 bytes/packet, 2x buffered.
3.7 External Interface
The SX2 presents two interfaces to the external master.
1. A FIFO interface through which EP2, 4, 6, and 8 data flows.
2. A command interface, which is used to set up the SX2, read
status, load descriptors, and access Endpoint 0.
3.7.1 Architecture
The SX2 slave FIFO architecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories and
are controlled by FIFO control signals (IFCLK, CS#, SLRD,
SLWR, SLOE, PKTEND, and FIFOADR[2:0]).
The SX2 command interface is used to set up the SX2, read
status, load descriptors, and access Endpoint 0. The
command interface has its own READY signal for gating
writes, and an INT# signal to indicate that the SX2 has data to
be read, or that an interrupt event has occurred. The command
interface uses the same control signals (IFCLK, CS#, SLRD,
SLWR, SLOE, and FIFOADR[2:0]) as the FIFO interface,
except for PKTEND.
3.7.2 Control Signals
3.7.2.1 FIFOADDR Lines
The SX2 has three address pins that are used to select either
the FIFOs or the command interface. The addresses corre-
spond to the following table.
Table 3-3. FIFO Address Lines Setting
Address/Selection
FIFO2
FIFO4
FIFO6
FIFO8
COMMAND
RESERVED
RESERVED
RESERVED
FIFOADR2 FIFOADR1 FIFOADR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Document #: 38-08013 Rev. *E
Page 5 of 42
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