28F800F3 데이터 시트보기 (PDF) - Intel

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28F800F3

FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT

Intel 

FAST BOOT BLOCK DATASHEET

E

2.0 PRODUCT DESCRIPTION

This section describes the pinout and block

architecture of the device family.

to the 16-Mbit density. The family is available in

µBGA CSP and 56-lead SSOP packages. Pinouts

for the 8- and 16-Mbit components are illustrated in

Figures 1 and 2.

2.1 Pinouts

Intel’s Fast Boot Block flash memory family

provides upgrade paths in each package pinout up

2.2 Pin Description

The pin description table describes pin usage.

1 2 3 4 5 6 7 8 9 10

A

A15

A12

GND CLK VCC VPP

A4

A1

B

32M

16M

A14

A11

A8

A20 ADV# WE# A19

A17

A5

A2

C

64M

A13

A10

A9

A21 RST# WP# A18

A7

A6

A3

D

VCCQ DQ7 DQ13 DQ12 DQ4 DQ11 DQ10 DQ9 DQ0 CE#

E

A16 DQ15 DQ6 DQ5 VCC DQ3 DQ2 DQ1 OE#

A0

F

WAIT# GND DQ14 GND

VCCQ DQ8 GND

NOTES:

1. Shaded connections indicate upgrade address connections. Lower density devices will not have upper address solder

balls. Routing is not recommended in this area.

2. A20 and A21 are the upgrade address for potential 32-Mbit and 64-Mbit devices (currently not on road map).

3. Reference the Micro Ball Grid Array Package Mechanical Specification and Media Information on Intel’s World Wide Web

home page for detailed package specifications.

Figure 1. 56-Ball µBGA* Package Pinout (Top View, Ball Down)

6

PRODUCT PREVIEW

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