EL4581CS 데이터 시트보기 (PDF) - Elantec -> Intersil

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EL4581CS

Sync Separator, 50% Slice, S-H, Filter

Elantec -> Intersil 

EL4581C

Sync Separator 50% Slice S-H Filter

Description of Operation Contd

vertical sync pulse widths The internal timing

circuits are referenced to IOT and VR3 the time-

out period being inversely proportional to the

timing current The vertical output pulse is start-

ed on the first serration pulse in the vertical in-

terval and is then self-timed out In the absense

of a serration pulse an internal timer will default

the start of vertical

The back porch is triggered from the sync tip

trailing edge and initiates a one-shot pulse The

period of this pulse is again a function of IOT and

will therefore track the scan rate set by RSET

Block Diagram

The odd even circuit (O E) comprises of flip

flops which track the relationship of the horizon-

tal pulses to the leading edge of the vertical out-

put and will switch on every field at the start of

vertical Pin 7 is high during the odd field

Loss of video signal can be detected by monitor-

ing the C S output The 50% level of the previ-

ous video signal will remain held on the S H ca-

pacitors after the input video signal has gone and

the input on pin 2 has defaulted to the clamp

voltage Consequently the C S output will re-

main low longer than the normal vertical pulse

period An external timing circuit could be used

to detect this condition

Note RSET must be a 1% resistor

Figure 5

9

4581 – 4

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