MAX3270EMN 데이터 시트보기 (PDF) - Maxim Integrated
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MAX3270EMN
Maxim Integrated
MAX3270EMN Datasheet PDF : 12 Pages
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155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
______________________________________________________________Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15, 16
17, 19, 38,
39
18
20
21, 22, 34,
35, 36
23, 33, 37,
40, 43, 44
24, 27, 29,
32
25
26
28
30
31
41
42
NAME
GVEE
AVEE1
SDIP
SDIN
AVCC
FM
AVCC
FILG
FILP
FILN
VTTL
AVEE2
EXCS
EXC
AVCC
DVCC
CRS
RST
DVEE
N.C.
OVCC
RDON
RDOP
CRP
RCON
RCOP
PHADJ
VR
FUNCTION
Guard-Ring Negative Supply to Substrate: -4.5V
Negative Supply for Input Buffers: -4.5V
Serial Data Input: 155Mbps or 622Mbps. Differential ECL Positive.
Serial Data Input: 155Mbps or 622Mbps. Differential ECL Negative.
Ground for Input Buffers: 0V
Frequency Monitor Output. This pin monitors the input voltage to the VCO. When the PLL is locked,
the pin will be ≅ 0V.
Guard-Ring Positive Supply to Epi: 0V
Loop Filter Ground. This pin connects to an external filter.
Loop Filter Positive. This pin connects to an external filter.
Loop Filter Negative. This pin connects to an external filter.
TTL Positive Supply: +5.0V
Negative Supply for VCO: -4.5V
External Clock-Select TTL Input. A logical high selects the external clock.
External Clock. Single-ended ECL input.
Ground for VCO: 0V
Digital Ground for Mux: 0V
Clock-Rate Select TTL Input. This selects the clock rate to be either 155Mbps or 622Mbps. A logic-
high level selects the 622Mbps mode.
Resets all digital flip-flops, TTL input. Reset is assert when low.
Digital Negative Supply: -4.5V
No Connection
Output Driver Ground: 0V
Negative Recovered Data Output, differential ECL output: 155Mbps or 622Mbps.
Positive Recovered Data Output, differential ECL output: 155Mbps or 622Mbps.
Clock-Reference Output Divide-by-4. ECL low-power single-ended: 38Mbps or 155Mbps.
Negative Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps.
Positive Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps.
Phase Adjust. This is an analog adjustment that varies the static phase between the input data and
the recovered clock. If not used, this input should be grounded. The range is from -1V to 1V.
Phase Reference Voltage: 0V. The PHADJ pin compares to this voltage. Set to ground.
6 _______________________________________________________________________________________
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