MAX3270EMN 데이터 시트보기 (PDF) - Maxim Integrated

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MAX3270EMN

155Mbps/622Mbps Clock Recovery and Data Retiming IC with Fully Integrated Phase/Frequency Detector

Maxim Integrated 

155Mbps/622Mbps Clock Recovery and

Data Retiming IC with Fully Integrated

Phase/Frequency Detector

Input and Output Termination

The MAX3270 data and clock I/Os (SDIP, SDIN, RDOP,

RDON, RCOP, RCON, and EXC) are open emitters,

designed to interface with ECL signal levels. It is impor-

tant to bias these ports appropriately. A circuit that pro-

vides a Thevenin equivalent of 50Ω to -2V should be

used with fixed-impedance transmission lines for prop-

er termination. Figure 4 shows some typical input and

output termination methods.

The serial data input signals (SDIP and SDIN) are the

differential inputs to an emitter coupled pair. As a result,

the MAX3270 can accept differential input signal levels

as low as 250mV. The serial input (SDIP) can also be

driven single-ended by externally biasing SDIN to the

center of the voltage swing (approximately -1.3V). Make

sure that the differential inputs and outputs each see the

same termination impedance for balanced operation.

CRP is also an open-emitter ECL output, but it requires

a termination resistor of 450Ω to -4.5V. If this output is

not used, reduce power by connecting CRP to VEE

through a resistor valued at 10kΩ or more.

The MAX3270’s performance can be greatly affected

by circuit board layout and design. Use good high-fre-

quency design techniques, including minimizing

ground inductances and using fixed-impedance trans-

mission lines on the data and clock signals. Power-

supply decoupling should be placed as close to the

VEE and VTTL pins as possible. AVEE1, AVEE2 and

GVEE should each have their own bypass/decoupling

elements, independent of each other and any other -

4.5V supply. Make sure to isolate the inputs from the

outputs to reduce feedthrough.

__________Applications Information

Lock Detection

The MAX3270 has an output (FM) that monitors the input

voltage to the VCO. FM is an analog output that can be

used as a flag to indicate that the PLL is locked. Under

normal operation, the loop is locked and the FM output

is approximately equal to 0V. When the PLL is unlocked,

the VCO will drift. The FM output monitors this drift and

will equal approximately ±1V in the limit.

Phase Adjust

In some applications, the optimum alignment point

between the recovered clock and the serial data is not

at the center of the eye diagram. The MAX3270 has a

PHADJ input that can be used in these applications to

introduce a phase difference between the recovered

clock and the serial data. When no phase difference is

desired, this input should be set to 0V. The VR pin is the

reference input for PHADJ and is normally tied to GND.

Zo = 50Ω

Zo = 50Ω

50Ω 50Ω

-2V

ECL

INPUTS ECL

OUTPUTS

MAX3270

CRP

Zo = 50Ω

Zo = 50Ω

50Ω 50Ω -2V

450Ω

90.9Ω

90.9Ω

Zo = 50Ω

Zo = 50Ω

-4.5V 111Ω 111Ω

-4.5V

MAX3270

ECL

INPUTS ECL

OUTPUTS

90.9Ω

Zo = 50Ω

Zo = 50Ω

90.9Ω

111Ω 111Ω -4.5V

CRP

450Ω

50Ω to -2V TERMINATION

-4.5V

THEVENIN EQUIVALENT TERMINATION

Figure 4. Typical Input and Output Terminations

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