HAL525 데이터 시트보기 (PDF) - Unspecified

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HAL525

Hall Effect Sensor IC

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HAL525, HAL535

2. Functional Description

The Hall effect sensor is a monolithic integrated circuit

that switches in response to magnetic fields. If a mag-

netic field with flux lines perpendicular to the sensitive

area is applied to the sensor, the biased Hall plate

forces a Hall voltage proportional to this field. The Hall

voltage is compared with the actual threshold level in

the comparator. The temperature-dependent bias

increases the supply voltage of the Hall plates and

adjusts the switching points to the decreasing induc-

tion of magnets at higher temperatures. If the magnetic

field exceeds the threshold levels, the open drain out-

put switches to the appropriate state. The built-in hys-

teresis eliminates oscillation and provides switching

behavior of output without bouncing.

Magnetic offset caused by mechanical stress is com-

pensated for by using the “switching offset compensa-

tion technique”. Therefore, an internal oscillator pro-

vides a two phase clock. The Hall voltage is sampled

at the end of the first phase. At the end of the second

phase, both sampled and actual Hall voltages are

averaged and compared with the actual switching

point. Subsequently, the open drain output switches to

the appropriate state. The time from crossing the mag-

netic switching level to switching of output can vary

between zero and 1/fosc.

Shunt protection devices clamp voltage peaks at the

Output-pin and VDD-pin together with external series

resistors. Reverse current is limited at the VDD-pin by

an internal series resistor up to −15 V. No external

reverse protection diode is needed at the VDD-pin for

reverse voltages ranging from 0 V to −15 V.

Reverse

1

Voltage &

Overvoltage

VDD Protection

Temperature

Dependent

Bias

Hysteresis

Control

Short Circuit

and

Overvoltage

Protection

Hall Plate

Switch

Comparator

Output

3

OUT

Clock

2

GND

Fig. 2–1: HAL525, HAL535 block diagram

fosc

t

B

BON

t

VOUT

VOH

VOL

t

IDD

1/fosc = 9 µs

Fig. 2–2: Timing diagram

tf

t

Micronas

5

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