HM64YLB36514BP-6H 데이터 시트보기 (PDF) - Renesas Electronics
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HM64YLB36514BP-6H
Renesas Electronics
HM64YLB36514BP-6H Datasheet PDF : 22 Pages
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HM64YLB36514 Series
AC Characteristics (Ta = 0 to +85°C, VDD = 2.5 V ± 5%)
Single Differential Clock Register-Latch Mode
HM64YLB36514BP
-6H
Parameter
Symbol Min
Max
Unit Notes
CK clock cycle time
tKHKH
6.5
ns
CK clock high width
tKHKL
1.2
ns
CK clock low width
tKLKH
1.2
ns
Address setup time
t
0.4
AVKH
ns 2
Data setup time
t
0.4
DVKH
ns 2
Address hold time
t
1.0
KHAX
ns
Data hold time
tKHDX
1.0
ns
Clock high to output valid
tKHQV
1.7
5.5
ns 1
Clock low to output valid
tKLQV
0.5
2.3
ns
Clock low to output hold
tKLQX
0.5
ns
Clock low to output low-Z (SS control)
tKLQX2
0.5
ns 1, 4, 6
Clock high to output high-Z
tKHQZ
0.5
2.3
ns 1, 3, 6
Output enable low to output low-Z
tGLQX
0.1
ns 1, 4, 6
Output enable low to output valid
t
GLQV
2.3
ns 1, 4
Output enable high to output high-Z
t
GHQZ
2.3
ns 1, 3
Sleep mode recovery time
t
20.0
ZZR
ns 5
Sleep mode enable time
tZZE
15.0
ns 1, 3, 5
Notes: 1. See figure in ”AC Test Conditions”.
2. Parameters may be guaranteed by design, i.e., without tester guardband.
3. Transitions are measured ±50 mV of output high impedance from output low impedance.
4. Transitions are measured ±50 mV from steady state voltage.
5. When ZZ is switching, clock input K must be at the same logic level for the reliable operation.
6. Minimum value is verified by design and tested without guardband.
Rev.0.10, May.15.2003, page 10 of 22
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