HM64YLB36514BP-6H 데이터 시트보기 (PDF) - Renesas Electronics

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HM64YLB36514BP-6H

16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit, Register-Latch Mode)

Renesas Electronics 

HM64YLB36514 Series

Notes: 1. Bit#1 is the first scan bit to exit the chip.

2. The NC pads listed in this table are indeed no connects, but are represented in the boundary

scan register by a “Place Holder”. Place holder registers are internally connected to VSS.

3. In boundary scan mode, differential input K and K are referenced to each other and must be at

the opposite logic levels for the reliable operation.

4. ZZ must remain V during boundary scan.

IL

5. In boundary scan mode, ZQ must be driven to VDDQ or VSS supply rail to ensure consistent results.

6. M1 and M2 must be driven to VDD, VDDQ or VSS supply rail to ensure consistent results.

ID Register

Part

HM64YLB36514

Revision

number

(31:28)

0000

Device density

and configuration

(27:18)

0011100100

Vendor

definition

(17:12)

000000

Vendor JEDEC

code (11:1)

00000000111

Start

bit (0)

1

TAP Controller State Diagram

1

Test-logic-

reset

0

0

Run-test/ 1

idle

Select- 1

DR-scan

0

1

Capture-DR

0

Shift-DR

0

1

Exit1-DR 1

0

Pause-DR

0

1

0

Exit2-DR

1

Update-DR

1

0

Select- 1

IR-scan

0

1

Capture-IR

0

Shift-IR

0

1

Exit1-IR 1

0

Pause-IR

0

1

0 Exit2-IR

1

Update-IR

1

0

Note:

The value adjacent to each state transition in this figure represents the signal present at TMS at the

time of a rising edge at TCK.

No matter what the original state of the controller, it will enter Test-logic-reset when TMS is held

high for at least five rising edges of TCK.

Rev.0.10, May.15.2003, page 20 of 22

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