ICS9160-03 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9160-03 Datasheet PDF : 7 Pages
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ICS9160-03
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
2
3
1
4
5, 6, 7
8, 9, 11, 12
10, 17
13
PIN NAME
X1
X2
VDDX
GNDX
FS(0:2)
PCLK(0:3)
VDDP
GNDP
14
SDATA
15, 16
18
19, 21, 22, 24,
25, 27, 28
20
23
26
29
30
31
32
STOP(0:1)
REFCLK
BCLK(0:6)
GNDB
VDDB
GNDF
VDDF
FLOPPY
KEYBD
GRAPHIC
TYPE
IN
OUT
PWR
IN
OUT
PWR
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
DESCRIPTION
XTAL or external reference frequency input. This input includes XTAL load
capacitance and feedback bias for a 10-30 MHz XTAL.**
XTAL output which includes XTAL load capacitance.**
XTAL oscillator circuit and REFCLK output power supplies.
Frequency selection address pins. These inputs have pull-ups.
Processor clock outputs which are a multiple of the input reference frequency as
shown in the table below.
PCLK power supplies. VDDP powers the internal PCLK PLL and the
PCLK(0:3) outputs.
Serial stop clock data is clocked in on the falling edge of BCLK. A total of 15 bits
must be clocked in using the following protocol. SDATA is sampled on the falling
edge of BCLK, so the data generator should change data on the rising edge of
BCLK to ensure proper communication. SDATA must be low for one BCLK period
as a start bit. The next 15 rising edges of BCLK will clock data in serially. The
16th clock enables the serial data to take effect. Outputs associated with serial data
bits that are a one will continue without interruption. Clocks associated with serial
data bits that are a zero will be stopped in the low state glitch-free, that is, no short
clocks with the exception of REFCLK and KEYBD which do not stop. This input
has an internal pull-up device.
Stop clock control pins used for glitch-free start and stop of the clock outputs as
described in the table on the next page. These inputs have internal pull-up devices.
Buffered copy of the crystal reference frequency.
Bus clock outputs having selectable frequency based on the FS(0:2) inputs (see
table on next page).
BCLK power supplies. VSSB and VDDB power BCLK(0:6).
Fixed clock power supplies. VSSF and VDDF power GRAPHIC, FLOPPY and
KEYBD outputs plus the fixed clock PLL.
The floppy clock output operates at 24 MHz..*
The keyboard clock output operates at 12 MHz.*
The graphics system clock output operates at 40 MHz.*
* Frequencies assuming an input or crystal of 14.318 MHz.
** Device provides 18pF load capacitance for crystal.
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