ICS9160M-03 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS9160M-03 Datasheet PDF : 7 Pages
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ICS9160-03
Preliminary Product Preview
The data is latched into the internal shift register on the falling edge of the BCLK signal with the BCLK as a reference
(see waveform above). The SDATA input pattern will change at the BCLK rising edges and must be stable for loading into
the shift register at the BCLK falling edges.
Programming Bit Addresses
The following table lists the function of each of the 15 input programming bits for the device.
ICS9160-03 SDATA Serial Stop Clock Input Pin Bit Pattern
BIT#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUTPUT PIN
32
n/a
30
28
27
21
22
24
25
19
n/a
12
11
9
8
STOP CLOCK FUNCTION
(Clocks stops if Bit=Low)
START BIT (One "zero" bit needed to start shift register sequence.)
GRAPHIC
FLOPPY
BCLK6
BCLK5
BCLK4
BCLK3
BCLK2
BCLK1
BCLK0
PCLK3
PCLK2
PCLK1
PCLK0
6
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