ICS9169AM-70 데이터 시트보기 (PDF) - Integrated Device Technology
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ICS9169AM-70 Datasheet PDF : 7 Pages
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VDD = 3.3±10%, TA = 0 to 70°C
Crystal = 14.31818MHz
SCSI outputs: SCSI(0:2)
(Assume divide by 2 from VCO)
FS2B
0
0
0
0
1
1
1
1
FS1B
0
0
1
1
0
0
1
1
FS0B
0
1
0
1
0
1
0
1
Target
MHz
24
48
10
20
40
50
60
80
Actual
MHz
24
48.07
10.02
20.05
40.09
50.11
60.14
80.18
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
PCI outputs: PCI (0:8)
(Assume divide by 2 from VCO)
FS2A
0
0
0
0
1
1
1
1
FS1A
0
0
1
1
0
0
1
1
FS0A
0
1
0
1
0
1
0
1
Target
MHz
Tristate
REF/2
30
33.3
50
55
60
66.6
Actual
MHz
Tristate
REF/2
30.07
33.27
50.11
54.89
60.14
66.63
REF
MHz
Tristate
REF
14.318
14.318
14.318
14.318
14.318
14.318
Note: When FS(0:2)A is 000 or 001, the Tristate and
Test modes applies to all outputs for REF, PCI, and
SCSI outputs.
FS2A
0
0
FS1A
0
0
FS0A
0
1
PCI SCSI REF
Tristate Tristate Tristate
REF/21 REF/21 REF1
Note: 1. In Test mode, each PLL is bypassed. The clock
signal at X1 (externally driven clock or the
crystal) is applied to the divider circuits.
3
ICS9169A-70
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