FCT162511AT 데이터 시트보기 (PDF) - Integrated Device Technology

부품명

상세내역

제조사

FCT162511AT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

Integrated Device Technology 

IDT54/74FCT162511AT/CT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

Symbol

Description

VTERM(2) Terminal Voltage with Respect to

GND

VTERM(3) Terminal Voltage with Respect to

GND

TSTG Storage Temperature

Max.

–0.5 to +7.0

–0.5 to

VCC +0.5

–65 to +150

Unit

V

V

°C

IOUT DC Output Current

–60 to +120 mA

NOTES:

2916 lnk 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

2. Open drain and all device terminals except FCT162XXXT Output and I/O

terminals.

3. Output and I/O terminals for FCT162XXXT.

FUNCTION TABLE(1,4)

OEAB

Inputs

LEAB CLKAB

Outputs

Ax

Bx

H

X

X

X

Z

L

H

X

L

L

L

H

X

H

H

L

L

↑

L

L

L

L

↑

H

H

L

L

L

X

B(2)

L

L

H

X

B(3)

NOTES:

2916 tbl 02

1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,

LEBA, and CLKBA.

2. Output level before the indicated steady-state input conditions were

established.

3. Output level before the indicated steady-state input conditions were

established, provided that CLKAB was HIGH before LEAB went LOW.

4. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don't Care

Z = High Impedance

↑ = LOW-to-HIGH Transition

PIN DESCRIPTION

Pin Names

OEAB

OEBA

Description

A-to-B Output Enable Input (Active LOW)

B-to-A Output Enable Input (Active LOW)

LEAB

A-to-B Latch Enable Input

LEBA

B-to-A Latch Enable Input

CLKAB

A-to-B Clock Input

CLKBA

B-to-A Clock Input

Ax

A-to-B Data Inputs or B-to-A 3-State Outputs

Bx

PERA

PERB

B-to-A Data Inputs or A-to-B 3-State Outputs

Parity Error (Open Drain) on A Outputs

Parity Error (Open Drain) on B Outputs

PAx(1)

A-to-B Parity Input, B-to-A Parity Output

PBx

ODD/EVEN

GEN/CHK

B-to-A Parity Input, A-to-B Parity Output

Parity Mode Selection Input

A to B Port Generate or Check Mode Input

NOTES:

2916 tbl 03

1. The PAx pin input is internally disabled during parity generation. This

means that when generating parity in the A to B direction there is no need

to add a pull up resistor to guarantee state. The pin will still function

properly as the parity output for the B to A direction.

5.11

4

Share Link: