IDT72401 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT72401 Datasheet PDF : 9 Pages
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IDT72401, IDT72402, IDT72403, IDT72404
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
TIMING DIAGRAMS (Continued)
(2)
SHIFT OUT
(3)
SHIFT IN
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(5)
INPUT READY (1)
INPUT DATA
(4)
tPT
t IPH
t SIR
t HIR
STABLE DATA
NOTES:
1. FIFO is initially full.
2. Shift Out pulse is applied.
3. Shift In is held HIGH.
4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented. Shift In should not go LOW until (tPT + tIPH).
Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH
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1/fOUT
1/fOUT
SHIFT OUT
tSOH
t SOL
(2)
OUTPUT READY
tODH
tODS
t ORL
OUTPUT DATA
A-DATA
(1)
NOTES:
1. This data is loaded consecutively A, B, C.
2. Data is shifted out when Shift Out makes a HIGH to LOW transition.
B-DATA
Figure 5. Output TIming
tORH
C-DATA
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SHIFT OUT(7)
OUTPUT READY
(2)
(1)
(4)
(5)
(3)
(6)
OUTPUT DATA
A-DATA
B-DATA
A or B
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NOTES:
1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.
2. Shift Out goes HIGH causing the next step.
3. Output Ready goes LOW.
4. The read pointer is incremented.
5. Output Ready goes HIGH indicating that new data (B) is now available at the FIFO outputs.
6. If the FIFO has only one word loaded (A DATA) then Output Ready stays LOW and the A DATA remains unchanged at the outputs.
7. Shift Out pulses applied when Output Ready is LOW will be ignored.
Figure 6. The Mechanism of Shifting Data Out of the FIFO
5.01
6
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