IMC004FLSA-ET15 데이터 시트보기 (PDF) - Intel

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IMC004FLSA-ET15

SERIES 2 FLASH MEMORY CARDS

Intel 

SERIES 2 FLASH MEMORY CARDS

Symbol

A0 – A25

DQ0 – DQ15

CE1 CE2

OE

WE

RDY BSY

CD1 CD2

WP

VPP1 VPP2

VCC

GND

REG

RST

WAIT

BVD1 BVD2

RFU

NC

VS1 VS2

Table 2 Series 2 Flash Memory Card Pin Descriptions

Type

Name and Function

I

ADDRESS INPUTS A0 through A25 are address bus lines which enable direct

addressing of 64 megabytes of memory on a card A0 is not used in word

access mode A24 is the most significant address bit Note A25 is a no-connect

but should be provided on host side

I O DATA INPUT OUTPUT DQ0 through DQ15 constitute the bidirectional data

bus DQ15 is the most significant bit

I

CARD ENABLE 1 2 CE1 enables even bytes CE2 enables odd bytes

Multiplexing A0 CE1 and CE2 allows 8-bit hosts to access all data on DQ0

through DQ7 (See Table 3 for a more detailed description )

I

OUTPUT ENABLE Active low signal gating read data from the memory card

I

WRITE ENABLE Active low signal gating write data to the memory card

O READY BUSY OUTPUT Indicates status of internally timed erase or write

activities A high output indicates the memory card is ready to accept

accesses A low output indicates that a device(s) in the memory card is(are)

busy with internally timed activities See text for an alternate function (READY-

BUSY MODE REGISTER)

O CARD DETECT 1 2 These signals provide for correct card insertion detection

They are positioned at opposite ends of the card to detect proper alignment

The signals are connected to ground internally on the memory card and will be

forced low whenever a card is placed in the socket The host socket interface

circuitry shall supply 10K or larger pull-up resistors on these signal pins

O WRITE PROTECT Write Protect reflects the status of the Write-Protect switch

on the memory card WP set high e write protected providing internal

hardware write lockout to the flash array

WRITE ERASE POWER SUPPLY (12V nominal) for erasing memory array

blocks or writing data in the array They must be 12V to perform an erase write

operation

CARD POWER SUPPLY (5V nominal) for all internal circuitry

I

GROUND for all internal circuitry

I

REGISTER SELECT provides access to Series 2 Flash Memory Card registers

and Card Information Structure in the Attribute Memory Plane

I

RESET from system active high Places card in Power-On Default State

RESET pulse width must be t 200 ns

O WAIT (Extend Bus Cycle) is used by Intel’s I O cards and is driven high

O BATTERY VOLTAGE DETECT Upon completion of the power on reset cycle

these signals are driven high to maintain SRAM-card compatibility

RESERVED FOR FUTURE USE

NO INTERNAL CONNECTION Pin may be driven or left floating

VOLTAGE SENSE Notifies the host Socket of the card’s VCC requirements

VS1 and VS2 are both open indicating a 5V VCC card

3

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