IMC020FLSA-15 데이터 시트보기 (PDF) - Intel

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IMC020FLSA-15

SERIES 2 FLASH MEMORY CARDS

Intel 

SERIES 2 FLASH MEMORY CARDS

PCMCIA JEIDA INTERFACE

The Series 2 Flash Memory Card interface supports

the PCMCIA 2 1 and JEIDA 4 1 68-pin card format

(see Tables 1 and 2) Detailed specifications are de-

scribed in the PC Card Standard Release 2 1 July

1993 published by PCMCIA The Series 2 Card con-

forms to the requirements of both Release 1 and

Release 2 of the PC Card Standard

Series 2 Card pin definitions are equivalent to the

Bulk-Erase Flash Card except that certain No Con-

nects are now used A22 through A24 RST (Reset)

and RDY BSY (Ready Busy) have pin assign-

ments as set by the PCMCIA standard

NOTE The READY BUSY signal is abbreviated as

RDY BSY by PCMCIA (card level) and as

RY BY by JEDEC (component level)

The outer shell of the Series 2 card meets all

PCMCIA JEIDA Type 1 mechanical specifications

See Figure 19 for mechanical dimensions

WRITE PROTECT SWITCH

A mechanical write protect switch provides the

card’s memory array with internal write lockout The

Write-Protect (WP) output pin reflects the status of

this mechanical switch It outputs a high signal (VOH)

when writes are disabled This switch does not lock

out writes to the Component Management Regis-

ters

BATTERY VOLTAGE DETECT

PCMCIA requires two signals BVD1 and BVD2 be

supplied at the interface to reflect card battery con-

dition Flash Memory Cards do not require batteries

When the power on reset cycle is complete BVD1

and BVD2 are driven high to maintain compatibility

CARD DETECT

Two signals CD1 and CD2 allow the host to de-

termine proper socket seating They reside at oppo-

site ends of the connector and are tied to ground

within the memory card

DESIGN CONSIDERATIONS

The Series 2 Card consists of two separate memory

planes the Common Memory Plane (or Main Memo-

ry) and the Attribute Memory Plane The Common

Memory Plane resides in the banks of device pairs

and represents the user-alterable memory space

The Component Management Registers (CMR) and

the hardwired Card Information Structure (CIS) re-

side in the Attribute Memory Plane within the Card

Control Logic as shown in Figure 3 The Card Con-

trol Logic interfaces the PCMCIA connector and the

internal flash memory array and performs address

decoding and data control

Attribute Memory Plane

accessible with

REG (pin 61) e VIL

INTEL e Performance Enhancement Register

PCMCIA e Defined in PCMCIA Release 2 0

290434 – 2

Figure 3 Component Management Registers Allow S W Control of Components within Card

7

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