IS42S16400-7T 데이터 시트보기 (PDF) - Integrated Circuit Solution Inc

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IS42S16400-7T

2(1)M Words x 8(16) Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Circuit Solution Inc 

IS42S8800/IS42S8800L

IS42S16400/IS42S16400L

Precharge

The precharge command can be asserted anytime after tRAS(min.) is satisfied.

Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters

the idle state after tRP(min.) is satisfied. The parameter t RP is the time required to perform the precharge.

The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as

follows.

PrechargeE

CLK

Command

CAS latency = 2

DQ

Burst lengh=4

T0

T1

T2

T3

T4

T5

T6

T7

Read

PRE

Q0

Q1

Q2

Q3

Hi - Z

Command

CAS latency = 3

DQ

Read

PRE

Hi - Z

Q0

Q1

Q2

Q3

(tRAS is satisfied)

In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL(min.)

specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be

calculated by dividing tDPL(min.) with the clock cycle time.

In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is

valid. In the following table, minus means clocks before the reference; plus means time after the reference.

CAS latency

2

3

Read

-1

-2

Write

+ tDPL((min.)

+ tDPL((min.)

Integrated Circuit Solution Inc.

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DR007-0A

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