ISL24006 데이터 시트보기 (PDF) - Intersil

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ISL24006

14-Channel Programmable Switchable I2C TFT-LCD Reference Voltage Generator with Integrated 4-Channel Static Gamma Drivers

Intersil 

ISL24006

Absolute Maximum Ratings (TA = 25°C)

Supply Voltage between AVDD and GND . . . . . . . . . . . . . . . . .+18V

Supply Voltage between DVDD and GND lesser of VS or +7V (max)

Maximum Continuous Output Current . . . . . . . . . . . . 20mA/channel

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD

Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The device outputs cannot withstand short-

circuit condition for extended periods of time. To avoid damage, do not exceed absolute maximum rating of 20mA/channel.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Electrical Specifications AVDD = 15V, DVDD = 5V, VREFU_H = 14V, VREFU_L = 8.5V, VREFL_H = 6.5V, VREFL_L = 1V, RL = 1kΩ and

CL = 10pF to 1/2 AVDD, TA = 25°C, unless otherwise specified.

PARAMETER

DESCRIPTION

CONDITIONS

MIN TYP MAX UNIT

SUPPLY

IAVDD

IDVDD

ANALOG

Supply Current

Digital Supply Current

No load

30

38

mA

2.75

4

mA

VOH

VOL

VOH

VOL

PSRR

VAC

IB

REG

BG

OUT1 to OUT7

OUT1 to OUT7

OUT8 to OUT14

OUT8 to OUT14

Power Supply Rejection Ratio

Accuracy

Input Bias Current,

VREF(U_H, U_L, L_H, L_L)

Load Regulation

Band Gap

VREFU_H = 14V, AVDD = 15V

VREFU_L = 8.5V, AVDD = 15V

VREFL_H = 6.5V, AVDD = 15V

VREFL_L = 1.0V, AVDD = 15V

AVDD is moved from 14V to 16V

VREF = 1/2 AVDD

IOUT = 5mA step

13.94 13.98 14.02

V

8.47 8.51 8.55

V

6.44 6.48 6.52

V

0.96 1.00 1.04

V

42

50

dB

-50

0

+50

mV

2

50

nA

0.5

mV/mA

1.1

1.3

1.4

V

SR

Slew Rate

8

15

V/µs

tS

DIGITAL

Settling Time

±1/2 LSB

1

µs

VIH

Logic 1 Input Voltage

DVDD-

V

20%

VIL

FCLK

RSDIN

tS

tH

Logic 0 Input Voltage

Clock Frequency

SDIN Input Resistance

Setup Time

Hold Time

SCL, SDA, STD_REG

20%*

V

DVDD

400

kHz

1

GΩ

40

ns

40

ns

2

FN6110.1

September 9, 2005

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