K6E0808C1C-TC12 데이터 시트보기 (PDF) - Samsung
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K6E0808C1C-TC12 Datasheet PDF : 8 Pages
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PRELIMINARY
K6E0808C1C-C
CMOS SRAM
32K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 12, 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL) : 40mA(Max.)
(CMOS) : 2mA(Max.)
Operating K6E0808C1C-12 : 165mA(Max.)
K6E0808C1C-15 : 150mA(Max.)
K6E0808C1C-20 : 140mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Standard Pin Configuration
K6E0808C1C-J : 28-SOJ-300
K6E0808C1C-T : 28-TSOP1-0813. 4F
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A3
A4
A5
A6
A7
A8
A12
A13
A14
I/O1~I/O8
Data
Cont.
Pre-Charge-Circuit
Memory Array
512 Rows
64x8 Columns
I/O Circuit
Column Select
CLK
Gen.
A0 A1 A2 A9 A10 A11
CS
WE
OE
GENERAL DESCRIPTION
The K6E0808C1C is a 262,144-bit high-speed Static Random
Access Memory organized as 32,768 words by 8 bits. The
K6E0808C1C uses 8 common input and output lines and has
an output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6E0808C1C is packaged
in a 300mil 28-pin plastic SOJ or TSOP1 forward.
PIN CONFIGURATION(Top View)
OE
1
A11
2
A9
3
A8
4
A13
5
WE
6
Vcc
7
A14
8
A12
9
A7
10
A6
11
A5
12
A4
13
A3
14
TSOP1
28
A10
27
CS
26
I/O8
25
I/O7
24
I/O6
23
I/O5
22
I/O4
21
Vss
20
I/O3
19
I/O2
18
I/O1
17
A0
16
A1
15
A2
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
SOJ
28 Vcc
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CS
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
PIN FUNCTION
Pin Name
A0 - A14
WE
CS
OE
I/O1 ~ I/O8
VCC
VSS
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
-2-
Rev 4.0
February 1998
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