KK82C55 데이터 시트보기 (PDF) - Kodenshi Auk Co., LTD
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KK82C55 Datasheet PDF : 22 Pages
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TECHNICAL DATA
KK82C55
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
The Integral KK82C55AN is a high-performance, CHMOS version of the industry standard
KK82C55AN general purpose programmable I/O device which is designed for use with all Intel and
most other microprocessors. It provides 24 I/O pins which may be individually programmed in 2
groups of 12 and used in 3 major modes of operation.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or
outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the
remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bi-
directional bus configuration.
FEATURES
• Compatible with all Intel and Most Other Microprocessors
• High Speed, «Zero Wait State» Operation with 8MHz 8086/88 and 80186/188
• 24 Programmable I/O Pins
• Low Power CHMOS
• Completely TTL Compatible
• Control Word Read-Back Capability
• Direct Bit Set/Reset Capability
• 2.5mA DC Drive Capability on all I/O Port Outputs
• Available in 40-Pin DIP
• Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
GROUP
A
CONTROL
D7-D0
DATA
BUS
BUFFER
8 BIT
INTERNAL
DATA BUS
RD
WR
A1
A0
Reset
CS
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
Figure 1
GROUP
A
PORT
A
(8)
GROUP
A
PORT C
UPPER
(4)
GROUP
B
PORT C
LOWER
(4)
GROUP
B
PORT
B
(8)
PA7-PA0
PC7-PC4
PC3-PC0
PB7-PB0
PA3
PA2
PA1
PA0
RD
CS
VSS
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
1.
40
2.
39
3.
38
4.
37
5.
36
6.
35
7.
34
8.
33
9.
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
Figure 2
PA4
PA5
PA6
PA7
WR
Reset
D0
D1
D2
D3
D4
D5
D6
D7
VCC
PB7
PB6
PB5
PB4
PB3
1
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