LH28F800BG-L 데이터 시트보기 (PDF) - Sharp Electronics
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LH28F800BG-L Datasheet PDF : 43 Pages
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LH28F800BG-L/BGH-L (FOR TSOP, CSP)
BLOCK ORGANIZATION
This product features an asymmetrically-blocked
architecture providing system memory integration.
Each erase block can be erased independently of
the others up to 100 000 times. For the address
locations of the blocks, see the memory map in
Fig. 1.
Boot Blocks : The two boot blocks are intended to
replace a dedicated boot PROM in a micro-
processor or microcontroller-based system. The
boot blocks of 4 k words (4 096 words) feature
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot blocks is
controlled using a combination of the VPP, RP# and
WP# pins.
BLOCK DIAGRAM
Parameter Blocks : The boot block architecture
includes parameter blocks to facilitate storage of
frequently update small parameters that would
normally require an EEPROM. By using software
techniques, the byte-rewrite functionality of
EEPROMs can be emulated. Each boot block
component contains six parameter blocks of 4 k
words (4 096 words) each. The parameter blocks
are not write-protectable.
Main Blocks : The reminder is divided into main
blocks for data or code storage. Each 8 M-bit
device contains fifteen 32 k words (32 768 words)
blocks.
DQ0-DQ15
OUTPUT
BUFFER
INPUT
BUFFER
A0-A18
INPUT
BUFFER
Y
DECODER
ADDRESS
LATCH
ADDRESS
COUNTER
X
DECODER
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
Y GATING
15
32 k-WORD
MAIN BLOCKS
COMMAND
USER
INTERFACE
I/O
LOGIC
VCC
CE#
WE#
OE#
RP#
WP#
WRITE
STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
RY/BY#
VPP
VCC
GND
-3-
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