LH28F800BG-L 데이터 시트보기 (PDF) - Sharp Electronics
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LH28F800BG-L Datasheet PDF : 43 Pages
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system to read data from, or write to any other
flash memory array location.
The boot block is located at either the top or the
bottom of the address map in order to
accommodate different micro-processor protect for
boot code location. The hardware-lockable boot
block provides complete code security for the
kernel code required for system initialization.
Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 4.9 for
details). Block erase or word write for boot block
must not be carried out by WP# to low and RP# to
VIH.
The status register indicates when the WSM’s block
erase or word write operation is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase or word write.
RY/BY#-high indicates that the WSM is ready for a
new command, block erase is suspended (and
word write is inactive), word write is suspended, or
the device is in deep power-down mode.
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
The access time is 85 ns (tAVQV) at the VCC supply
voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70°C (LH28F800BG-L)/
– 40 to +85°C (LH28F800BGH-L). At 4.5 to 5.5 V
VCC, the access time is 90 ns or 120 ns. At lower
VCC voltage, the access time is 100 ns or 130 ns
(3.0 to 3.6 V) and 120 ns or 150 ns (2.7 to 3.6 V).
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
5 V VCC and 3 mA at 2.7 V and 3.3 V VCC.
When CE# and RP# pins are at VCC, the ICC
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
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