M24C64-WMW6 데이터 시트보기 (PDF) - STMicroelectronics
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M24C64-WMW6 Datasheet PDF : 19 Pages
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M24C64, M24C32
Figure 4. I2C Bus Protocol
SCL
SDA
START
CONDITION
SDA
SDA
INPUT CHANGE
STOP
CONDITION
SCL
SDA
1
2
3
MSB
START
CONDITION
7
8
9
ACK
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP
CONDITION
AI00792
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9th clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I2C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the mem-
ory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9th bit time. If the memory does not match
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