MAX1446(2003) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1446
(Rev.:2003)

10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference

Maxim Integrated 

10-Bit, 60Msps, 3.0V, Low-Power

ADC with Internal Reference

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected

to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz

(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design

and characterization.Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Input Low Threshold

Input Hysteresis

Input Leakage

Input Capacitance

DIGITAL OUTPUTS (D9–D0)

Output Voltage Low

VIL

VHYST

IIH

IIL

CIN

CLK

PD, OE

VIH = VDD = OVDD

VIL = 0

VOL

ISINK = 200µA

0.2 x

VDD

V

0.2 x

OVDD

0.1

V

±5

µA

±5

5

pF

0.2

V

Output Voltage High

Three-State Leakage Current

VOH

ILEAK

ISOURCE = 200µA

OE = OVDD

OVDD -

0.2

V

±10

µA

Three-State Output Capacitance COUT OE = OVDD

5

pF

POWER REQUIREMENTS

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Output Supply Current

Power-Supply Rejection

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid

OE Fall to Output Enable

OE Rise to Output Disable

CLK Pulse Width High

VDD

OVDD

IVDD

IOVDD

PSRR

CL = 10pF

Operating, fIN = 19.943MHz at -0.5dBFS

Shutdown, clock idle, PD = OE = OVDD

Operating, CL = 15pF, fIN = 19.943MHz at

-0.5dBFS

Shutdown, clock idle, PD = OE = OVDD

Offset

Gain

tDO

tENABLE

tDISABLE

Figure 5 (Note 3)

Figure 5

Figure 5

tCH

Figure 6, clock period 16ns

2.7

3.0

3.6

V

1.7

3.0

3.6

V

30

37

mA

4

15

µA

7

mA

1

20

µA

± 0.1

mV/V

± 0.1

%/V

5

8

ns

10

ns

1.5

ns

8.3

± 2.5

ns

CLK Pulse Width Low

tCL

Figure 6, clock period 16ns

8.3

± 2.5

ns

Wake-Up Time

tWAKE (Note 4)

1.5

µs

Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a +1.024V full-scale

input voltage range.

Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is

6dB better, if referenced to the two-tone envelope.

Note 3: Digital outputs settle to VIH, VIL.

Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.

4 _______________________________________________________________________________________

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